Author: gfieni

This week I spent a large amount of my time working on the design report. The first few days of the week I spent writing about half of the report in order for Xiran to be able to edit it later. While I was able to draw from our slides, much of the work for the report was expanding on the details mentioned in the presentation. I also looked through the feedback given to us from both the students and the instructors to ensure that their concerns were addressed in the report. I also made some final revisions on the report before we turned it in.

Ali and I also worked on getting the NOIS II ethernet demo working. We ran into a lot of issues this week in trying to run the demo. Firstly, the different versions of Quartus that we have on the lab computers versus the Quartus Lite that Ali has on her laptop have caused some discrepancies between the program we are trying to setup. I think that we are close to being able to run the demo on the board. However, this has been a much more laborious process than expected and unforeseen setbacks could keep popping up. Our hope is that once we get the demo to run, we can modify the code from the demo to do what we need.

Given this difficulty, we also have been investigating other methods for getting our input and output to and from the board in case we need to abandon the ethernet protocol. We have about 2MB of memory on the DE2-115 FPGA board, which we are looking into using to preload our inputs to the program.

This upcoming week, I will also be working on the Ethics assignment and adding an Ethics section to our design report for the final.

This week Ali and I again focused on understanding the NOIS II processor on the FPGA boards. Unfortunately, we were halted from initiating some of our work due to delays in having access to equipment we needed in order to run some of the demos. However, once we were able to connect to the board using Ethernet, we worked through some of the demos that come with the DE2-115 FPGA board. We were unable to run the demo we wanted to run because we need an internet gateway, which we do not have and do not want to buy since we won’t need it for our project. However, even without being able to actually run the demo, we were able to see how the NOIS II actually is implemented on the board and how to access its own command line. We also investigated more about how Quartus interfaces with the NOIS II, something that we will need to continue to look into this upcoming week.

I also spent some time at the beginning of the week preparing for the design presentation, since I was our group’s presenter. On Sunday night, I did a few dry runs and really tried to prepare a good narrative for our project. Xiran and Ali were kind enough to watch and give me some very valuable feedback.

I also started working on the design report at the end of the week. I’m planning on spending most of the early part of this week focusing on the design report.

Other than the design report, Ali and I plan on actually running the NOIS II processor on our board this week to create a communication protocol. We will most likely need more time than expected to finish this task.

This week Ali and I focused on researching and testing different communication methods on the FPGA. We are already familiar with JTAG protocol methods, so we decided to focus on USB and Ethernet. I found that there are a bunch of demos already made specifically for the DE2-115 FPGA board that we will be using that implement different features of the board. One such test utilizes USB while another uses Ethernet. We were not able to actually run these demos together this week since we were waiting for the right cables to be ordered by the department. The demos are in chapter 6 in the manual (https://www.intel.com/content/dam/www/programmable/us/en/portal/dsn/42/doc-us-dsnbk-42-1404062209-de2-115-user-manual.pdf).

We also investigated how to use the triple speed Ethernet on the DE2-115 boards. I found that we will need to instantiate the NIOS II (a softcore microprocessor) on the board (using LUTs), which will connect to the 88E1111 Marvell PHY Chip on the board. I started looking through the documentation and short usage video chips on the NIOS II processor using their developer support tools (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). Unless we are willing to buy the license for the others, we will need to use the lowest performance NIOS II processor (version NIOS II/e).

I also worked a lot on the design slides for the next week’s presentations and did some practice runs as I will be the presenter for our group.

Additionally, our entire group worked together to determine which speeds we will need to meet for our project to meet its performance requirements. We ran some simulation tests and determined that we will need to use gigabit ethernet to achieve the necessary speeds.

Next week, Ali and I plan to run some of the demos and look through the code in the demos to see how they configure the NIOS II processor.

This week I focused on researching different communication protocols to be used for communicating between the PC and the FPGA board. I mainly researched Ethernet methods, but also looked at some USB ideas from my teammates. By comparing other thesis or final design projects from other universities, I found that there are methods for performing the tasks we need, but while Ethernet is very fast for performance metrics (can support 10Mbps, 100Mbps, and 1000Mbps), it is very difficult to implement in the DE2-115 Altera boards we are using (https://etd.ohiolink.edu/apexprod/rws_etd/send_file/send?accession=dayton1448287709&disposition=inline).
I discovered that one of the more challenging aspects of creating these protocols on this board is correctly using the NIOS II soft microprocessor. Both Xiran and I have embedded experience, so I am hopeful that by digging through the handbook for the NIOS II we will be able to effectively use it (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). We are also planning on reaching out to Bill Nace to see if he has any experience with NIOS II on these specific boards.
This upcoming week we want to test different protocols (if possible) using basic “ping” style tests. I found that the DE2-115 boards have demos in their manual kits that use both USB and Ethernet protocols. We are hoping to try to use those this week to learn how the built in tools work. I am currently on schedule for my deliverables. We are planning on meeting this week as a team to decide which method to use in our project.

This week I focused on helping our team finalize our project idea. We came into the week bouncing a few more ideas around until our meeting with Tamal and Joel. Based off of their suggestions, we decided to focus on the general idea of using FPGA prototyping to speedup simulation. Using our experiences in 18-447, we decided to focus on a debugging assistance tool that can compare the output of the DUT on the FPGA with a software golden model cycle-by-cycle. We realized that our most important design decision would be deciding how we communicated with the DUT to feed it input and receive the output. As such, I researched and conferred with my teammates on different methods of sending data.

To gain some more advice, we met with Professor Bill Nace to discuss the attributes of the Altera FPGA boards available in the lab. Based off of his guidence, this upcoming week will have us focus on testing different communication systems (usb, ethernet, etc.) with the FPGA. We are hoping that by the end of the next few weeks, we have modeled an efficient method of sending input and receiving output.