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Team Status Report for 10/2

The most significant risk that could jeopardize the success of the project is still in the communication protocol. Last Sunday, we made the decision to use Ethernet for communication. This week, while waiting for the Ethernet cable to arrive, Grace and Ali prepped by spending considerable time researching the protocol, including how the 88E1111 Marvell PHY Chip is connected to the board and its Ethernet ports. Next week, Grace and Ali will implement the protocol. We also plan to try out USB demos in the case of running into unresolvable issues with Ethernet.

The risk of the design not fitting on the board is also being managed. The finalized DUT ISA is intentionally small to mitigate this risk. In addition, we are looking into how much space the NIOS II processor takes up on the FPGA, so we can get a concrete number of how much is left for the DUT.

As for changes to our project, we worked on strengthening our project motivation and the requirements based on Proposal Presentation feedback. Instead of motivating solely with runtime gains, we will also highlight, in the future, how the FPGA approach allows the design to be tested in actual silicon instead of only in software. We also added a requirement of being able to support test cases of size 1 ~ 20k instructions, as a quantitative measure of what we can support was missing in the Proposal.

We do note that some of Grace’s and Ali’s work with Ethernet have been delayed due to waiting for equipment, but work will pick up next week. We may update the schedule next week depending on progress, but at the present, there are no changes.

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Ali’s Status Report for 10/2

This week I worked with Grace to learn more about the Ethernet ports on the FPGAs. Initially, we planned to run through the last demo that came with the DE2-115 boards (the demos can be found in the user manual – chapter 6). Because we were waiting for a USB-USB cable and a dual ended ethernet cable to come, we did not have the chance to run the demo. I am planning on running the demo later today or tomorrow. We were hoping to see a little bit more about what exactly using the ethernet port looks like in reality.

Because we were waiting to receive the cables, I spent most of Monday/Tuesday trying to look for resources on ethernet on our FPGA. Grace found information about the NIOS II processor which is a processor that runs on the FPGA’s internal components and makes it easier for users to interact with the components on the FPGA. I found this tutorial on creating a processor with the Triple Speed Ethernet ports (TSN Ethernet). I started walking through the tutorial on Wednesday to try to understand more about the process, but again, I couldn’t test it with the board because we received the cables on Thursday or Friday. A lot of my time this week was spent trying to find more resources on the TSN Ethernet ports, but there don’t seem to be too many resources. However, I did find the manual for the ethernet ports.

Lastly, I spent time research projects people have developed using the TSN ethernet and I tried to find some github projects with TSN ethernet, but I could only find people’s documentation not github repos. Most of our progress was hindered because we had to wait for our cables to come.

I also worked with Grace and Xiran to run tests on simulation to have a better idea of how long it takes to run some of these tests. I think we are a little behind where we wanted to be — I was hoping we would have been able to run some tests on the FPGA, but I am confident that we’ll be able to implement the ethernet protocol. Grace and I are probably going to meet Monday afternoon and work on the protocols some more. We are planning on looking through some of the code for the NIOS II processor to try to understand more about how the processor works, and how to correctly interface with the ethernet ports.

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Ali’s Status Report for 9/25

I spent this week focusing on 2 things:  preparing for the proposal presentation, and also researching the JTAG protocol. I spent a decent amount of time making sure that I was ready to present and could have a decent presentation.

Next, I spent time trying to understand more about the I/O protocols that the DE2-115 FPGA can manage. I found the user manual and started investigating how to debug JTAG vs USB vs Ethernet. It seems like JTAG has some of the expected benefits and detriments — easy to use, but might not be fast enough. Typically, JTAG can transfer data at a rate between 10 MHz and 100 MHz. Although this might be fast enough to send data in 1 direction, it might not be able to support sending enough data from the FPGA to the PC.

I think I am a little behind schedule, but I am planning on finishing up research and playing around with an FPGA early this week, and then working with Grace to develop the communication protocol.

For next week, I’m hoping to have finished or nearly finished the FPGA protocol.

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Team Status Report for 9/18

For our project, the most important design requirement is the runtime for completing tests. This runtime will consist of three components: the time it takes to send test cases to the FPGA, to actually process the tests through the DUT, and to send results back from the FPGA. Given that the FPGA runs on a fast hardware clock, we don’t expect the second component to take long. Instead, our bottleneck (and our biggest risk) will be in the communication latency to and from the FPGA.

For the next few weeks, we plan to focus our efforts on managing this risk. We will research different communication protocols available to us, pick some to implement, then pick one that meets our requirements through benchmarking.

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Ali’s Status Report for 9/18

This week I spent most of my time trying to research new ideas for our project. I spent a lot of time trying to find new papers discussing the benefits of FPGAs while also looking through the papers Xiran and Grace sent, and trying to evaluate the feasibility of the ideas. On Wednesday we finally settled on an idea, and we realized that we have only used FPGAs where we were providing inputs in the design via the switches and buttons on the board. But, we wanted to be able to send data to the FPGA from the computer while still using an Altera FPGA. I found a paper which discussed the feasibility of using ethernet to send data from the computer (Data Transfer System for Host Computer and FPGA Communication) which assured us that our idea could be possible.

On Friday, the three of us met with Prof. Nace to discuss the feasibility of our idea a little more. He confirmed that we should be able to use the Altera FPGAs and that he thought our idea had some interesting applications.

Next week, I want to continue to investigate how to send data from the computer to the FPGA, and visa versa because this is our biggest bottleneck right now. Next week, we are hoping to decide on the best method to send/receive data, and also potentially speak with Prof. Hoe because his research area is related to our project.