Grace’s Status Report for 9/25

This week I focused on researching different communication protocols to be used for communicating between the PC and the FPGA board. I mainly researched Ethernet methods, but also looked at some USB ideas from my teammates. By comparing other thesis or final design projects from other universities, I found that there are methods for performing the tasks we need, but while Ethernet is very fast for performance metrics (can support 10Mbps, 100Mbps, and 1000Mbps), it is very difficult to implement in the DE2-115 Altera boards we are using (https://etd.ohiolink.edu/apexprod/rws_etd/send_file/send?accession=dayton1448287709&disposition=inline).
I discovered that one of the more challenging aspects of creating these protocols on this board is correctly using the NIOS II soft microprocessor. Both Xiran and I have embedded experience, so I am hopeful that by digging through the handbook for the NIOS II we will be able to effectively use it (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). We are also planning on reaching out to Bill Nace to see if he has any experience with NIOS II on these specific boards.
This upcoming week we want to test different protocols (if possible) using basic “ping” style tests. I found that the DE2-115 boards have demos in their manual kits that use both USB and Ethernet protocols. We are hoping to try to use those this week to learn how the built in tools work. I am currently on schedule for my deliverables. We are planning on meeting this week as a team to decide which method to use in our project.