This week we made significant improvement in our communication protocol. Ali was able to finally load the NIOS II processor on the FPGA board successfully and do an Ethernet echo. We also learned that we can use the NIOS II/f (fast) instead of the NIOS II/e (economy) due to the fact that our DUT takes up less than 1% of the LUTs on the FPGA and the /f takes up only 8% of the LUTs on the board. This is promising because it would allow for much larger designs than our own to be tested on the board with the same processor.
Right now, we are still figuring out how to interface with the memory (SRAM) on the board. We need to be able to read/write from 1) the NIOS II to SRAM, and 2) the SV DUT to SRAM. We have been doing research into how to accomplish these tasks and want to implement a simple memory echo program using a SV design in the next week.