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Grace’s Status Report for 11/6

This past week Ali and I focused on getting Ethernet up and running. We were able to actually run the ethernet demo for the DE2-115 board, but the demo requires two cables (and we only had one). Therefore, we know how to run things using the NIOS, but we don’t believe that this is exactly what we will need for our project. Instead of sending data through the processor, I think we will need to send data through sockets that are connected on the processor and the PC. Ali has been looking into this method to see how to set it up using the NIOS. We should be able to do it pretty easily if the software tools on the lab machines allow us to run certain tasks.

This week was also spent prepping for the demo. We are hoping to have communication working in order to show it during our demo. Note, this is not the communication for the whole project, but a basic message sent back and forth to showcase functionality.

This upcoming week will be spent focusing on the demo and getting communication to work.

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Ali’s Status Report for 11/6

On Wednesday, Grace and I tried to adapt the demo to work for our FPGA with 1 ethernet cable. We succeeded, but with a caveat. We realized that the demo sends data down 1 ethernet cable, and then it bounces back on the other ethernet cable (originally, the demo used 2 ethernet cables). Additionally, when we type into the NIOS Console, we are actually sending commands from the processor (which makes sense), so when we were inputting a string to send, it was just us telling the processor what to transmit. This meant that we were not sending the FPGA data as we thought we were doing. I quickly searched how we can send data to the FPGA via ethernet using C, and it looks like we’ll need to use sockets. Sockets enable both devices to communicate with each other via a port. According to the Intel Forums, we should be able to use the Web Server Demo (a demo file from Quartus II) and the Simple Socket Server code (part of Eclipse SBT) to create a socket server. My plan for later tonight/tomorrow is to try to run this on the lab machines (unfortunately, I cannot install Quartus II on my computer, so I’m hoping to play around with it on the lab machines and then recreate it on Quartus Prime Lite which I have).

If this does not work, we will probably switch to JTAG UART using a serial cable. This would also be beneficial because Professor Nace runs a lab in 18-240 where 2 FPGAs communicate with each other via a serial cable. The backup plan is probably to have the processor handle reading and writing to the testcase/results file. We could then find a way to transmit that file to the PC (either using an SD card or maybe sending it back to the computer using JTAG). NOTE: If we decided to use UART, we would probably need yet another adapter to connect USB to Serial communication. (Sadly, JTAG UART is 9600 bits/sec). Also, I think it is still known that Ethernet/communication is behind. I’ll probably post a comment on this post today or tomorrow with the outcome of being in lab.