This week we decided to turn to serial communication in order to have a working data communication between the FPGA board and the PC. We are not completely abandoning ethernet, but want to have a working version first. In that vein, Ali and I were able to have access to 18-240’s serial communication lab from Bill Nace. This lab has one FPGA send bits serially to another FPGA. We had to wait for a serial cable in order to start implementing this lab (and then our actual protocol), so I spent the middle of the week researching more about serial communication, and in particular, UART. I took 18-349, so I am already pretty familiar with UART and USART. As long as we can ensure our timing is correct in translation between the baud rate on the PC and the clock frequency on the board, we shouldn’t have major issues implementing a basic serial protocol. A good, simple UART reference can be found here – it shows the basics for how UART works and the frames used in the most common protocols.
On Saturday, Ali and I spent the day in the lab implementing the serial lab and then started working on our own serial protocol. We are hoping to finish it up this week so that we can actually communicate with our DUT on the board.
This week, we plan to complete this protocol. The added bonus of UART is that it is well documented and a common protocol which should make it easier for us to implement.