This past week, I worked on the output end of our framework. I updated our golden model and DUT so that they now both read from a test case file and write cycle-by-cycle register dumps to output files. The output comparator that compares the two’s output files is also complete. Once again, the code can be found in our repo.
Save for communication between the PC and FPGA, our system flow is now complete! The user can create a test case using the test case generator, get the expected output from the golden model, get the DUT’s actual output from simulation (we can also synthesize the DUT but can’t talk to it yet), and compare outputs using the output comparator. I will be demoing these components.
I am on schedule. Starting next week, I will be exploring ways to make our UI more friendly. Also worthy of mentioning is that before the demo next week, I want to make a graph showing how simulation scales as test case size grows.