Our main risk is Ethernet communication again because we need to have both a laptop and the FPGA connected on the same socket. We’re going to see if Ali/Grace can get the socket code working on the lab machines this weekend. If not, they might switch to serial communication via JTAG UART. (This is currently the best option because we know that we can use the NIOS Processor now). There is also a chance that they can use the SD Card reader to send/receive the test cases/results. Ali asked Prof. Nace if he can share any information he has on the 18-240 lab which uses Serial Communication between FPGAs.
Also for the rest of the system, Xiran has made prototypes for all the components. She will be looking into how to make the components more user friendly in the next few weeks.