On Wednesday, Grace and I tried to adapt the demo to work for our FPGA with 1 ethernet cable. We succeeded, but with a caveat. We realized that the demo sends data down 1 ethernet cable, and then it bounces back on the other ethernet cable (originally, the demo used 2 ethernet cables). Additionally, when we type into the NIOS Console, we are actually sending commands from the processor (which makes sense), so when we were inputting a string to send, it was just us telling the processor what to transmit. This meant that we were not sending the FPGA data as we thought we were doing. I quickly searched how we can send data to the FPGA via ethernet using C, and it looks like we’ll need to use sockets. Sockets enable both devices to communicate with each other via a port. According to the Intel Forums, we should be able to use the Web Server Demo (a demo file from Quartus II) and the Simple Socket Server code (part of Eclipse SBT) to create a socket server. My plan for later tonight/tomorrow is to try to run this on the lab machines (unfortunately, I cannot install Quartus II on my computer, so I’m hoping to play around with it on the lab machines and then recreate it on Quartus Prime Lite which I have).
If this does not work, we will probably switch to JTAG UART using a serial cable. This would also be beneficial because Professor Nace runs a lab in 18-240 where 2 FPGAs communicate with each other via a serial cable. The backup plan is probably to have the processor handle reading and writing to the testcase/results file. We could then find a way to transmit that file to the PC (either using an SD card or maybe sending it back to the computer using JTAG). NOTE: If we decided to use UART, we would probably need yet another adapter to connect USB to Serial communication. (Sadly, JTAG UART is 9600 bits/sec). Also, I think it is still known that Ethernet/communication is behind. I’ll probably post a comment on this post today or tomorrow with the outcome of being in lab.
Update on going to lab: Last night I went, and I was able to open the demo on the lab machines, and I saved the system file as a newer version which would be compatible with my quartus. However, I ran into 2 problems. 1) The Lab machines do not have eclipse installed which means that I cannot use SBT for Eclipse (this is ok because there’s a console that can be used to download the demo on the board). However, it is definitely much more difficult to figure out what I am doing. Regardless, I was almost able to get the sockets demo working on the lab machines, but I couldn’t figure out the IP address of the FPGA. 2) I spent part of today trying to reconfigure the design which worked for Quartus II to work on my Quartus. Unfortunately, when I went to build the design, I ran into the same issues from before where Eclipse couldn’t find the header files. I added them to the includes lists, but they still don’t work. (I can hard code the paths, and that works, but then I’d have to edit some of Altera’s header files which isn’t ideal). I might poke around with this later tonight.