Posted on

Team Status Report for 10/9

There were no design changes or new risks to our project. However, we would like to note some schedule changes. (The updated schedule is provided below).

This week, Grace and Ali fell a little behind schedule due to waiting for the Ethernet dongle to arrive and lack of time to sync up after Wednesday. In the meantime, they focused on finding more resources and examples of people using the Nios II processor. Due to this setback, we are extending the tasks related to the communication protocol by a week. Next week, the goal for Grace and Ali is to complete a fairly simple test to verify 1) the Nios II processor is functional and 2) we can make use of it to send data back and forth.

Xiran’s work is on-time, with no adjustments to her schedule. To keep the ball rolling on the project, she will begin working on the DUT by herself next week. We may adjust the schedule for the DUT because it was originally planned to be a group effort.

Updated schedule

 

Posted on

Grace’s Status Report for 10/9

This week Ali and I again focused on understanding the NOIS II processor on the FPGA boards. Unfortunately, we were halted from initiating some of our work due to delays in having access to equipment we needed in order to run some of the demos. However, once we were able to connect to the board using Ethernet, we worked through some of the demos that come with the DE2-115 FPGA board. We were unable to run the demo we wanted to run because we need an internet gateway, which we do not have and do not want to buy since we won’t need it for our project. However, even without being able to actually run the demo, we were able to see how the NOIS II actually is implemented on the board and how to access its own command line. We also investigated more about how Quartus interfaces with the NOIS II, something that we will need to continue to look into this upcoming week.

I also spent some time at the beginning of the week preparing for the design presentation, since I was our group’s presenter. On Sunday night, I did a few dry runs and really tried to prepare a good narrative for our project. Xiran and Ali were kind enough to watch and give me some very valuable feedback.

I also started working on the design report at the end of the week. I’m planning on spending most of the early part of this week focusing on the design report.

Other than the design report, Ali and I plan on actually running the NOIS II processor on our board this week to create a communication protocol. We will most likely need more time than expected to finish this task.

Posted on

Ali’s Status Report for 10/9

This week Grace and I worked on understanding how to actually work with the Nios II Processor a bit. Because we were waiting to receive the USB-ethernet dongle, so we could more easily work with the ethernet ports, we were set back from originally working together Monday evening. On Wednesday, Grace and I sat down to try to follow the basic ethernet web-server demo that comes with the board. Unfortunately, we were 1) missing a gateway (which we didn’t realize we needed for the demo), and 2) missing a file which we think we needed to run the demo. However, we did play around with the Nios II SOPC builder a bit more this week, so we/I have a better understanding of how the processor actually works and how to build it. I also looked into the Nios II terminal which we can use to send data to the board via the ethernet connection. We have to do a little bit more research to understand if there is a way we can interface with the terminal, but at the very least, we know that we should be able to execute some sort of script that can execute the code within a test. Additionally, I spent a decent portion of time trying to reinstall quartus on my laptop, so that I can play around with ethernet from my computer. (It turns out that since Altera does not sign their drivers, and I have windows 11, it was difficult to figure out how to get around that issue)

I was hoping we would be able to run an actual test this week using the ethernet cable, but we spent a lot of time still digging up papers and resources to better understand how we will interface with it. I found a paper which interfaces ethernet (via the Nios II processor) with other code, so I feel like I have a better understanding of how we can utilize the processor and utilize our DUT at the same time. I think Grace and I are a little more behind than we wanted to be, but we’re aiming to spend a lot of time together Monday evening/maybe Wednesday figuring out a large portion of the ethernet and getting a simple test working. Next week, I’m planning on spending a lot of time making sure we can get ethernet working and helping out with the design report.

Posted on

Xiran’s Status Report for 10/9

This week, I implemented the golden model for our system. The code is in golden_model.c in our Github repo.

This C program reads an input test case file (containing instructions separated by end-of-line character) and computes the expected register values after each instruction. The program does not currently write the register dump to an output file, as we have not decided on the exact format of the output file yet, but I will add that once it’s been decided (this addition should not take long). I have also tested the golden model with different input files to verify its correctness.

My progress is on schedule. Next week, I expect to spend significant effort working on the design report. After that, I will start working on the SystemVerilog implementation of our DUT.

 

Posted on

Xiran’s Status Report for 10/2

This week, I transitioned from working on the communication portion of our project to working on the DUT. Namely, I finalized our ISA and designed the datapath for our DUT.

Designing the ISA involved several decisions: deciding 1) the number of bits, 2) the instruction format, and 3) the instructions themselves. For 1), I settled on 16 bits because it allows us to lesson the communication cost of the system, while still keeping the number large enough that it doesn’t become a toy example. For 2), I used the simplest scheme I could think of in the interest of making our instruction decoder simple, as is typical in a RISC architecture. For 3), I examined ISAs I have studied (x86, ARM, RISC-V) and chose 16 arithmetic/logical instructions that are in most ISAs, as these are the crucial ones.

Summary of our ISA

I also designed the datapath for our DUT: a single-cycle microarchitecture implementing this ISA. There aren’t many design decisions involved here. I simply chose the most simple datapath with my computer architecture knowledge.

DUT datapath block diagram

In addition to these individual tasks, I also worked on benchmarking simulation speed and the design review slides.

It should be noted that my action items did change this week from what I had planned. I originally planned to start working on the golden model this week, but given that it would be nice to have a concrete diagram of the DUT for the design review, I prefeteched the task of designing the datapath. However, I am still on track to meeting my deliverables. Next week, I will work on and finish the golden model.

Posted on

Team Status Report for 10/2

The most significant risk that could jeopardize the success of the project is still in the communication protocol. Last Sunday, we made the decision to use Ethernet for communication. This week, while waiting for the Ethernet cable to arrive, Grace and Ali prepped by spending considerable time researching the protocol, including how the 88E1111 Marvell PHY Chip is connected to the board and its Ethernet ports. Next week, Grace and Ali will implement the protocol. We also plan to try out USB demos in the case of running into unresolvable issues with Ethernet.

The risk of the design not fitting on the board is also being managed. The finalized DUT ISA is intentionally small to mitigate this risk. In addition, we are looking into how much space the NIOS II processor takes up on the FPGA, so we can get a concrete number of how much is left for the DUT.

As for changes to our project, we worked on strengthening our project motivation and the requirements based on Proposal Presentation feedback. Instead of motivating solely with runtime gains, we will also highlight, in the future, how the FPGA approach allows the design to be tested in actual silicon instead of only in software. We also added a requirement of being able to support test cases of size 1 ~ 20k instructions, as a quantitative measure of what we can support was missing in the Proposal.

We do note that some of Grace’s and Ali’s work with Ethernet have been delayed due to waiting for equipment, but work will pick up next week. We may update the schedule next week depending on progress, but at the present, there are no changes.

Posted on

Ali’s Status Report for 10/2

This week I worked with Grace to learn more about the Ethernet ports on the FPGAs. Initially, we planned to run through the last demo that came with the DE2-115 boards (the demos can be found in the user manual – chapter 6). Because we were waiting for a USB-USB cable and a dual ended ethernet cable to come, we did not have the chance to run the demo. I am planning on running the demo later today or tomorrow. We were hoping to see a little bit more about what exactly using the ethernet port looks like in reality.

Because we were waiting to receive the cables, I spent most of Monday/Tuesday trying to look for resources on ethernet on our FPGA. Grace found information about the NIOS II processor which is a processor that runs on the FPGA’s internal components and makes it easier for users to interact with the components on the FPGA. I found this tutorial on creating a processor with the Triple Speed Ethernet ports (TSN Ethernet). I started walking through the tutorial on Wednesday to try to understand more about the process, but again, I couldn’t test it with the board because we received the cables on Thursday or Friday. A lot of my time this week was spent trying to find more resources on the TSN Ethernet ports, but there don’t seem to be too many resources. However, I did find the manual for the ethernet ports.

Lastly, I spent time research projects people have developed using the TSN ethernet and I tried to find some github projects with TSN ethernet, but I could only find people’s documentation not github repos. Most of our progress was hindered because we had to wait for our cables to come.

I also worked with Grace and Xiran to run tests on simulation to have a better idea of how long it takes to run some of these tests. I think we are a little behind where we wanted to be — I was hoping we would have been able to run some tests on the FPGA, but I am confident that we’ll be able to implement the ethernet protocol. Grace and I are probably going to meet Monday afternoon and work on the protocols some more. We are planning on looking through some of the code for the NIOS II processor to try to understand more about how the processor works, and how to correctly interface with the ethernet ports.

Posted on

Grace’s Status Report for 10/2

This week Ali and I focused on researching and testing different communication methods on the FPGA. We are already familiar with JTAG protocol methods, so we decided to focus on USB and Ethernet. I found that there are a bunch of demos already made specifically for the DE2-115 FPGA board that we will be using that implement different features of the board. One such test utilizes USB while another uses Ethernet. We were not able to actually run these demos together this week since we were waiting for the right cables to be ordered by the department. The demos are in chapter 6 in the manual (https://www.intel.com/content/dam/www/programmable/us/en/portal/dsn/42/doc-us-dsnbk-42-1404062209-de2-115-user-manual.pdf).

We also investigated how to use the triple speed Ethernet on the DE2-115 boards. I found that we will need to instantiate the NIOS II (a softcore microprocessor) on the board (using LUTs), which will connect to the 88E1111 Marvell PHY Chip on the board. I started looking through the documentation and short usage video chips on the NIOS II processor using their developer support tools (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). Unless we are willing to buy the license for the others, we will need to use the lowest performance NIOS II processor (version NIOS II/e).

I also worked a lot on the design slides for the next week’s presentations and did some practice runs as I will be the presenter for our group.

Additionally, our entire group worked together to determine which speeds we will need to meet for our project to meet its performance requirements. We ran some simulation tests and determined that we will need to use gigabit ethernet to achieve the necessary speeds.

Next week, Ali and I plan to run some of the demos and look through the code in the demos to see how they configure the NIOS II processor.