This past week had substantial results for us as a group. In the beginning of the week, we were still hesitant that Ethernet could be configured correctly with the NIOS II processor. I started off the week investigating some of our risk mitigation strategies (as listed in the design report) incase we needed to shift toward a different communication protocol. However, by the middle of the week, Ali was able to load the NIOS II processor correctly. This shifted our focus to investigating the memory interface that the NIOS II works with. I began with reading through the DE2-115 FPGA manual and found that the board supports 2MB of SRAM, 128MB of SDRAM, and 8MB of Flash memory. Based off of the interfaces of each of these memory modules and descriptions of using each memory, SRAM was determined to be the easiest memory to use. Only 2 bytes of information can be read or written at the same time to SRAM and only a single type of transaction (read/write) can be done at a time. However, the memory does support a clock of up to 125 MHz, which means that we could read and write within one cycle on the FPGA by reading on the rising clock edge and writing on the falling clock edge of the FPGA’s 50 MHz clock. However, this method will have to be investigated more thoroughly.
I then continued to research more methods for reading and writing to SRAM within the SV program, which seems more difficult. I am still trying to find the correct way to interface with memory correctly in the program. I found this interesting tutorial, but it is interfacing with SDRAM. I was also reading through this message board to determine how the NIOS II can set memory in SRAM.
This upcoming week, Ali and I will need to investigate more about how to interact with the SRAM chip on the board and hopefully can interact with the memory through a SV program.