The most significant risk that could jeopardize the success of the project is still in the communication protocol. Last Sunday, we made the decision to use Ethernet for communication. This week, while waiting for the Ethernet cable to arrive, Grace and Ali prepped by spending considerable time researching the protocol, including how the 88E1111 Marvell PHY Chip is connected to the board and its Ethernet ports. Next week, Grace and Ali will implement the protocol. We also plan to try out USB demos in the case of running into unresolvable issues with Ethernet.
The risk of the design not fitting on the board is also being managed. The finalized DUT ISA is intentionally small to mitigate this risk. In addition, we are looking into how much space the NIOS II processor takes up on the FPGA, so we can get a concrete number of how much is left for the DUT.
As for changes to our project, we worked on strengthening our project motivation and the requirements based on Proposal Presentation feedback. Instead of motivating solely with runtime gains, we will also highlight, in the future, how the FPGA approach allows the design to be tested in actual silicon instead of only in software. We also added a requirement of being able to support test cases of size 1 ~ 20k instructions, as a quantitative measure of what we can support was missing in the Proposal.
We do note that some of Grace’s and Ali’s work with Ethernet have been delayed due to waiting for equipment, but work will pick up next week. We may update the schedule next week depending on progress, but at the present, there are no changes.