The biggest risk for our project remains to be the communication latency between the FPGA and the computer. This week, each of us researched one of three communication protocols under consideration (JTAG, USB, Ethernet). Tomorrow, we will meet to discuss choosing a protocol. Work on implementing the protocol will begin next week.
Another point of concern brought up during our Proposal Presentation is whether the size of our DUT will fit onto the FPGA. Work on designing the DUT ISA will also begin next week, and taking into account this feedback, we are considering limiting the design to an ALU. This will allow us to mitigate this risk.
There have been no changes to the requirements or the schedule.