This week I focused on researching different communication protocols to be used for communicating between the PC and the FPGA board. I mainly researched Ethernet methods, but also looked at some USB ideas from my teammates. By comparing other thesis or final design projects from other universities, I found that there are methods for performing the tasks we need, but while Ethernet is very fast for performance metrics (can support 10Mbps, 100Mbps, and 1000Mbps), it is very difficult to implement in the DE2-115 Altera boards we are using (https://etd.ohiolink.edu/apexprod/rws_etd/send_file/send?accession=dayton1448287709&disposition=inline).
I discovered that one of the more challenging aspects of creating these protocols on this board is correctly using the NIOS II soft microprocessor. Both Xiran and I have embedded experience, so I am hopeful that by digging through the handbook for the NIOS II we will be able to effectively use it (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). We are also planning on reaching out to Bill Nace to see if he has any experience with NIOS II on these specific boards.
This upcoming week we want to test different protocols (if possible) using basic “ping” style tests. I found that the DE2-115 boards have demos in their manual kits that use both USB and Ethernet protocols. We are hoping to try to use those this week to learn how the built in tools work. I am currently on schedule for my deliverables. We are planning on meeting this week as a team to decide which method to use in our project.
Ali’s Status Report for 9/25
I spent this week focusing on 2 things: preparing for the proposal presentation, and also researching the JTAG protocol. I spent a decent amount of time making sure that I was ready to present and could have a decent presentation.
Next, I spent time trying to understand more about the I/O protocols that the DE2-115 FPGA can manage. I found the user manual and started investigating how to debug JTAG vs USB vs Ethernet. It seems like JTAG has some of the expected benefits and detriments — easy to use, but might not be fast enough. Typically, JTAG can transfer data at a rate between 10 MHz and 100 MHz. Although this might be fast enough to send data in 1 direction, it might not be able to support sending enough data from the FPGA to the PC.
I think I am a little behind schedule, but I am planning on finishing up research and playing around with an FPGA early this week, and then working with Grace to develop the communication protocol.
For next week, I’m hoping to have finished or nearly finished the FPGA protocol.
Team Status Report for 9/25
The biggest risk for our project remains to be the communication latency between the FPGA and the computer. This week, each of us researched one of three communication protocols under consideration (JTAG, USB, Ethernet). Tomorrow, we will meet to discuss choosing a protocol. Work on implementing the protocol will begin next week.
Another point of concern brought up during our Proposal Presentation is whether the size of our DUT will fit onto the FPGA. Work on designing the DUT ISA will also begin next week, and taking into account this feedback, we are considering limiting the design to an ALU. This will allow us to mitigate this risk.
There have been no changes to the requirements or the schedule.
Xiran’s Status Report for 9/25
I spent this week researching FPGA communication protocols. I was assigned USB, so I started with that. I found the following key pieces of information from the DE2-115 User Manual:
- The board provides a USB device interface, supporting data transfer at 12 Mbit/s
- There’s a demo with complete driver code that connects the board to a host PC and allows the PC to control some components on the board (such as LEDs)
I dug for user-side information on this topic too (e.g., customized driver code) but was not able to find much. This lack of information makes the usability of USB concerning to me, so I also looked into Ethernet. Surprisingly, I was able to find an open-source Cornell project that implemented Ethernet communication to the board. This may be something we can use off the shelf.
I am on schedule for my deliverables. Next week, I will transition to designing the ISA for our DUT. My thoughts so far are to limit the design to an ALU that supports common arithmetic and logical instructions, but details (instruction format, number of registers, etc.) need to be worked out. By the end of next week, I plan to have the complete ISA and to have begun working on the software golden model that implements this ISA.
Team Status Report for 9/18
For our project, the most important design requirement is the runtime for completing tests. This runtime will consist of three components: the time it takes to send test cases to the FPGA, to actually process the tests through the DUT, and to send results back from the FPGA. Given that the FPGA runs on a fast hardware clock, we don’t expect the second component to take long. Instead, our bottleneck (and our biggest risk) will be in the communication latency to and from the FPGA.
For the next few weeks, we plan to focus our efforts on managing this risk. We will research different communication protocols available to us, pick some to implement, then pick one that meets our requirements through benchmarking.
Grace’s Status Report for 9/18
This week I focused on helping our team finalize our project idea. We came into the week bouncing a few more ideas around until our meeting with Tamal and Joel. Based off of their suggestions, we decided to focus on the general idea of using FPGA prototyping to speedup simulation. Using our experiences in 18-447, we decided to focus on a debugging assistance tool that can compare the output of the DUT on the FPGA with a software golden model cycle-by-cycle. We realized that our most important design decision would be deciding how we communicated with the DUT to feed it input and receive the output. As such, I researched and conferred with my teammates on different methods of sending data.
To gain some more advice, we met with Professor Bill Nace to discuss the attributes of the Altera FPGA boards available in the lab. Based off of his guidence, this upcoming week will have us focus on testing different communication systems (usb, ethernet, etc.) with the FPGA. We are hoping that by the end of the next few weeks, we have modeled an efficient method of sending input and receiving output.
Ali’s Status Report for 9/18
This week I spent most of my time trying to research new ideas for our project. I spent a lot of time trying to find new papers discussing the benefits of FPGAs while also looking through the papers Xiran and Grace sent, and trying to evaluate the feasibility of the ideas. On Wednesday we finally settled on an idea, and we realized that we have only used FPGAs where we were providing inputs in the design via the switches and buttons on the board. But, we wanted to be able to send data to the FPGA from the computer while still using an Altera FPGA. I found a paper which discussed the feasibility of using ethernet to send data from the computer (Data Transfer System for Host Computer and FPGA Communication) which assured us that our idea could be possible.
On Friday, the three of us met with Prof. Nace to discuss the feasibility of our idea a little more. He confirmed that we should be able to use the Altera FPGAs and that he thought our idea had some interesting applications.
Next week, I want to continue to investigate how to send data from the computer to the FPGA, and visa versa because this is our biggest bottleneck right now. Next week, we are hoping to decide on the best method to send/receive data, and also potentially speak with Prof. Hoe because his research area is related to our project.
Xiran’s Status Report for 9/18
I spent the majority of this week continuing to brainstorm project ideas. I looked into papers describing image processing and AI acceleration on FPGAs, before we settled on our idea on Wednesday. I then searched online and found many sources describing similar ideas (e.g., FPGA based accelerator for functional simulation, FPGA-accelerated evaluation and verification of RTL designs), which helped us confirm the validity of the use case and solution.
On Friday, I, along with my teammates, met with Prof. Bill Nace to discuss this idea further. I also set up the website. This weekend, I will help make the proposal slides. I am on schedule to meeting deliverables.
Next week, I will research communication protocols to send data to and obtain data from the FPGA. We should settle on one feasible protocol and begin implementing/benchmarking it.