- Work This Week
- Designed, programmed, and compiled the FPGA FSM and datapath, though it needs much debugging work.
- Got the simulation to run and wrote a testbench. The testbench did not work for a while due to syntax issues with ternary operations, but runs now and there are issues to debug.
- Helped look at EEPROM programming to set the chip to 245 asynchronous FIFO mode using 9V 3A power delivery.
- Schedule
- The code is slightly behind schedule, and I hope to finish debugging the FSM through simulation by this week so that integration goes smoothly by the end of this week or next week.
- By the interim demo, I hope to have a working FPGA code written. Although this cannot be demoed unless an FTDI chip and computer software is written. The basic sending data and receiving may be demonstrated as MVP.
- Next Week
- Finish debugging the full FPGA code through simulation.
- Help out in other tasks as necessary, and possibly integrate with code/FTDI chip/lasers.
Anju Ito, Roger Lacson, and KJ Newman