- This week
- Presented the design review for our team on Wednesday.
- Worked on slides and practices beforehand.
- Thought further about FPGA implementation, especially with regards to the interface between the FTDI chip.
- For the FTDI chip, I had some concerns about using a single fast serial data that splits into 2 serial data complicating timing. As a backup plan and knowing options, I looked into potential other modes that the FTDI chip supports, and found the asynchronous FIFO mode. This was the only other option that seemed reasonable to use, as others supplied a 60MHz clock (faster than the FPGA onboard and will probably not go through the GPIO pins smoothly). I plan on attempting to implement the FPGA with the fast serial, but as a backup go into FIFO if there are timing issues that become difficult to smooth out. In addition, if speed of the fast serial becomes a bottleneck, this can also potentially allow for a much faster interface between the FTDI buffer data and the FPGA.
- Thought through a little more of the block diagram and overall implementation, especially before the hardware arrives.
- My plan is to have a rough implementation of the FTDI side, since some aspects are difficult to predict without the actual hardware in hand. I plan on working and refining more of the actual laser side since that can be read with the oscilloscopes through the GPIO headers to verify actions.
- Helped focus the laser to verify that the laser beam angles can be fixed.
- Presented the design review for our team on Wednesday.
- Overall schedule
- I think that this week’s primary focus became the design review for the first few days. Although it’s not very far off schedule, I think that I could have worked on a more detailed implementation of the FPGA, which I plan on doing next week instead.
- Goal for next week
- Have an implementation of the laser side, and a rough idea of how the interface would be handled on the FTDI side on the FPGA.
Anju Ito, Roger Lacson, and KJ Newman