Month: April 2022

This week I worked on finishing the entirety of the AGC Assembler code for the AGC. This mostly consisted of a simple FSM-like loop that selects appropriate program to execute when a correct program number is entered. For instance, VERB 39 NOUN 1 will run a program to calculate the delta-v required to escape a planetary body’s gravitational field (escape velocity). Other programs include calculating translunar injection velocities, Hohmann transfer orbital transfers, and orbital plane transfers. Furthermore, we realized that the SQRT function from the Apollo missions used instructions which were descoped, therefore I had to implement a custom single precision square root subroutine. The sine functions from the Apollo missions are still being used for calculations.

My goal for next week is to finish validating the AGC program and debug on our SystemVerilog implementation. I also plan on working on finishing the Python demo visualizer.

Earlier this week, I assisted Christopher in debugging our CPU implementation to work with multiplication, division, augment, diminish, and increment instructions.  Although we reached a consensus that these instructions were working, we’ve discovered recently that our double-precision computations don’t work the same way as the yaYul simulator implementation.  For cleanliness, we have decided to forego changing our multiplier and divider circuits as well as adding a double precision adder.  I am currently writing those implementations in SystemVerilog in anticipation of verifying their correctness with example assembly programs. These changes will allow us to implement a CPU that meets the capabilities of our desired demo programs.  Following these changes, I will make updates to the I/O “register file” to support Jae’s desired I/O format, then implement the I/O serial interface.

I spent most of this week debugging the RTL. I got the rest of the test cases working this week and helped debug Jae’s code when it was running on the RTL simulation. I also changed the pipeline to support an instruction we did not previously think we were gonna use (DDOUBL). Next week I hope to start synthesizing our code and help Jae with any more debugging. I am on schedule but I doubt I will be able to do everything I need to do next week because of a dependency on Donny.

This week was spent mostly spent continuing to work on the demo programs for the AGC and studying more on the AXI-AGC interaction. For the demo, a simple visualization script running on Python will demonstrate the orbital mechanics calculations of the AGC. To do so, AXI will be used to send simulation mission data to the AGC, and after the AGC calculates required orbital delta-v or other parameters, will send the calculation results back to the AXI to the python script. I will be running a simple 3-body simulation of the Moon, Earth, and the space-craft. For the visualization library, I will most likely use matplotlib to plot a simple 3d motions of the planetary bodies and the spacecraft.

I will continue to work on finishing the DSKY firmware next week, especially since I am now aware of the I/O specifications from the AGC Verilog code. I will then finish up the AGC demo code.

I spent most of this week debugging the RTL. I compiled the finished portion of the RTL and resolved all the lint issues with my portion of the code. I then traced through the most basic test case I wrote INCR.agc. This test case branched then incremented a few addresses in memory before ending. Getting this test case to work required me to catch several bugs. One with the reset value of the pipeline registers, one with reading from ROM, a couple misconceptions in the addressing unit and in the pipeline and some issues in the decoder. According to the schedule Donny and I have one more week till we pass all the test cases. We are on schedule but need to stay work hard next week to stay on schedule.

I neglected to post the last couple of weeks, but most of my tasks have been long-term anyways.  I wrote the initial implementations of our CPU’s register file, arithmetic logic unit, memory address translation unit, and I/O unit a few weeks back.  Since then, a number of bugs with those units as well as the lower level computational units have been detected and addressed.  With our interim demo quickly approaching, I’ve started to run basic tests using simple assembly programs written by Christopher, each testing a specific subset of our instruction set.  Along with simple visual scans of Verilog implementations, a number of larger functional bugs have been identified and resolved.  As of now, basic arithmetic appears to be working fine, as well as memory loads and stores.  I plan to move on to writing test assembly programs for I/O instructions in anticipation of the interim demo.  Following that, I will begin implementing the I/O<->serial interface units.