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Team Status Report for 2/12

This week we were dealing with a few significant risks. The first one was the worry that our PCB would not be ready in time. In order to deal with that we started the layout this week and aim to be done with the preliminary layout in the coming week. Another risk was going into our project without knowing how to do every step and realizing some steps were much harder than we thought. We minimized this risk by doing more research into some of the details of our project so we could have a better idea about our implementation and it’s feasibility

We made some changes to the use case. Our use case is now a museum rather than for actual space travel. We made this change on the recommendation of our advisor. This changes a few things about our project. Firstly we are implementing more of the instruction set to stay more true to the original design. This will increase the difficulty of the cpu pipeline design and implementation (which will consume more time), but it does mean we will be able to use more of the original Apollo programs which will hopefully save us some time.

We started our PCB layout earlier than expected so our schedule now looks like this


A sneak preview of the schematic capture:

A link to our current cpu design is here https://app.diagrams.net/#G1K-aGTft1UyUYiGw6LQ5oJ6zeiqgNk8Xc

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Christopher’s Status Report for 2/12

This week I prepared for the proposal presentation and then gave the presentation. The bulk of the work I did was designing the cpu pipeline and making a detailed diagram about it. A second thing I did was doing research about the simulation and synthesis tool chain I would use to compile my processor the code I want to run on it and then simulate or synthesize it. Lastly I started the presentation slides for the design review. Thus far I am on schedule as my goal for the week was to design the cpu pipeline and finalize what my tool chain would look like for synthesis and simulation. The next week I hope to create the presentation slides and find an I2C verilog IP that we can use in our design.