This week, I finished the second part of our testing regime by synthesizing every module through terminal as well as using Quartus. I added synthesize commands to our Makefile and updated the FPGA module code such that any unsynthesizable logic was replaced. In particular, the top module took the most time because I was accessing the GPIO pins as a 36 wire block. However, this was causing issues because I needed both input and output functionality within a block. I ended up separating the wires out and only using the five that I needed to implement SPI. In addition, I hardcoded a Bitcoin block header into the code for testing. For now, the FPGA will cycle through all nonces until it reaches one that hashes below the target. Because the block header is preset, the communication aspect of the FPGA modules were not able to be tested.
I am still on schedule because most testing was finished this week.The FPGA side of the communication with the Raspberry Pi is complete but I am waiting on the Raspberry Pi side to be finished.
Next week, I will switch to working on the Raspberry Pi software and making sure that it is able to send and receive data. After this is complete, I can finish the FPGA testing by having a block header be sent over, the FPGA hashes it, and sends the correct nonce back to the Raspberry Pi.