Team Status Report for December 6

Team Status Report for December 6

What are the most significant risks that could jeopardize the success of the project? How are these risks being managed? What contingency plans are ready?

The most significant risk at this stage is integration issues between our hardware and software subsystems now that we have assembled PCBs. We’re managing this through systematic unit testing of each board subsystem before full integration. Our contingency plan includes having the previous revision boards available as backup if critical issues emerge with the new assembly.

Another risk is time pressure for final documentation and demo preparation. We’re mitigating this by working on documentation in parallel with testing rather than waiting until all testing is complete. This ensures we can deliver quality documentation even if late-stage issues require debugging time.

Were any changes made to the existing design of the system (requirements, block diagram, system spec, etc)? Why was this change necessary, what costs does the change incur, and how will these costs be mitigated going forward?

Yes, we made one significant design change this week: switching from a passive USB signal path to an active USB repeater board for signal integrity.

this was thought of a while ago, however we finally received our new usb boards.

Why this change was necessary: During our initial testing and analysis, we identified potential signal degradation issues with longer USB cable runs between the power cycling board and the target device. The passive approach would have limited our maximum cable length and potentially caused data recovery failures due to signal quality issues.

Costs incurred: The active repeater adds approximately $15 to our BOM cost and introduces an additional component that requires power and creates another potential failure point. It also adds slight complexity to our system integration.

Mitigation: The cost increase is well within our project budget. The reliability improvement significantly outweighs the added complexity, and active repeaters are well-characterized components with predictable behavior. This change actually reduces our overall risk by ensuring robust USB communication across various cable lengths and device types.

Provide an updated schedule if changes have occurred.

No schedule changes this week. We remain on track for final demo and report submission.

Unit Tests and System Tests

Unit Tests Conducted:

Power Delivery Subsystem:

  • Voltage regulation verification (5V rail within ±5% tolerance)
  • Current limiting functionality (verified 500mA limit)
  • Power cycling timing accuracy (on/off sequences within 10ms of specification)
  • Thermal performance under sustained load

USB Signal Path:

  • Signal integrity measurements
  • Data transmission verification at USB 2.0 speeds (480 Mbps)

Data Recovery Software Module:

  • PDF file structure parsing (cross-reference table handling)
  • File system metadata extraction
  • Recovery success rate with known test files

Overall System Tests:

Speed Testing:

  • Data transfer rates measured across full recovery pipeline
  • Average throughput: [results pending complete integration]

Latency Testing:

  • Power cycle to device enumeration time
  • End-to-end recovery process timing
  • Measured latency between power cycle initiation and data access

Recovery Rate Testing:

  • Success rate with various file types (PDF, DOCX, images)
  • Recovery reliability across different USB device types
  • Partial recovery capability for corrupted files

Findings and Design Changes:

 

Design Change Implemented: Replaced passive USB signal path with active USB repeater board. The active repeater provides signal regeneration and impedance matching, ensuring reliable USB 2.0 communication across cable lengths up to 5 meters.

Impact: This change improved our system’s robustness and expanded our operational range. Testing shows clean signal quality and reliable enumeration with the active repeater, resolving the signal integrity issues we identified.

Progress Photos

Our revision 2 PCBs are fully assembled and undergoing systematic testing. Initial power-on tests show all subsystems functioning within specification. The active USB repeater integration is complete and performing well in preliminary tests.

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