This week we finally got ADC triggering working properly. We managed to do this with a combination of timer synchronization and modifying the manufacturer timer driver function used for initialization. Because we are using center-aligned PWM as discussed in previous status reports, the timer’s counter counts from 0 to 1023 and back down to 0. Every time it reaches 0 or 1023 and changes direction, the timer generates an update event (“UEV” in the above diagram). This update event is used as a clock for another timer, eliminating the issue we previously encountered with timers running at different speeds despite running off the same clock source with the same prescalers. The secondary timer is running in edge-aligned upcounting mode with a maximum counter value of 1. Each time it overflows from 1 to 0 (i.e. on every other increment), the timer triggers the ADC reading.

The issue we encountered at this point was that the low side FETs are on the PWM complementary output, so they are active when the PWM counter is around 0. This means we want to trigger the ADC every time the PWM counter is around 0, which is on every other update event.

The PWM timer and secondary timer counters both start at 0. The PWM timer issues an update event upon activation, incrementing the secondary timer counter to 1. Then the PWM timer counts up to 1023, issues another update event, increments the secondary timer counter again, overflowing it to 0 and triggering the ADC. However, this means the ADC is triggering when the high side FETs are active (PWM timer at 1023), which is the opposite of what we want.

The easiest way to solve this is to reverse the starting direction of the PWM timer. It should issue an update event upon activation to increment the secondary timer counter to 1, then count down to 0, issue another update event, overflow the secondary timer, and trigger the ADC. As the PWM timer continues counting, the secondary timer will overflow and trigger the ADC on every other update event, which is every time the PWM timer reaches 0 (when the low side FETs are open). Unfortunately, the manufacturer’s timer drivers don’t support setting the initial counting direction of the timer, and the direction bit is read-only when the timer is configured in center-aligned mode. With some reading of the datasheet and the manufacturer’s initialization code, we were able to insert a few lines to allow us to start the PWM timer in downcounting mode.

We confirmed the ADCs were working with ROTATÉ, and measured the time between a couple interrupts (overflow of the secondary timer counter, and DMA transfer completion) by changing a GPIO pin in the interrupt handlers and using an oscilloscope. We then reduced the ADC sampling time when we found that the FETs were switching during sampling and affecting the measurements.