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==== Reading List (in reverse order) ==== | ==== Reading List (in reverse order) ==== | ||
+ | === 11/18/2014 === | ||
+ | Review required for the following paper, due on Tuesday, Nov 18. | ||
+ | * **Justin Meza et al., "Memory Errors at Scale: What the Trends Across a Billion-User Web Services Company Foretell", under submission. (Please do not distribute)** | ||
+ | |||
=== 11/13/2014 === | === 11/13/2014 === | ||
Reviews required for both papers, due on Wednesday, Nov 12. | Reviews required for both papers, due on Wednesday, Nov 12. | ||
* **[[http://dl.acm.org/citation.cfm?id=2503257|Sridharan et al., "Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults", SC 2013.]]** | * **[[http://dl.acm.org/citation.cfm?id=2503257|Sridharan et al., "Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults", SC 2013.]]** | ||
* [[https://www.cs.cmu.edu/~bianca/fast07.pdf|Bianca Schroeder, Garth A. Gibson, "Disk Failures in the Real World: What Does an MTTF of 1, 000, 000 Hours Mean to You?", FAST 2007.]] | * [[https://www.cs.cmu.edu/~bianca/fast07.pdf|Bianca Schroeder, Garth A. Gibson, "Disk Failures in the Real World: What Does an MTTF of 1, 000, 000 Hours Mean to You?", FAST 2007.]] | ||
+ | * [[http://www.pdl.cmu.edu/PDL-FTP/associated/dsn06.pdf|Bianca Schroeder, Garth A. Gibson, "A large-scale study of failures in high-performance computing systems", DSN 2006.]] | ||
* [[http://www.cs.toronto.edu/~hwang/papers/asplos2012.pdf|Andy A. Hwang, et al., "Cosmic rays don't strike twice: understanding the nature of DRAM errors and the implications for system design", ASPLOS 2012.]] | * [[http://www.cs.toronto.edu/~hwang/papers/asplos2012.pdf|Andy A. Hwang, et al., "Cosmic rays don't strike twice: understanding the nature of DRAM errors and the implications for system design", ASPLOS 2012.]] | ||
* [[http://static.googleusercontent.com/media/research.google.com/en/us/pubs/archive/35162.pdf|Bianca Schroeder et al., "DRAM Errors in the Wild: A Large-Scale Field Study", SIGMETRICS 2009.]] | * [[http://static.googleusercontent.com/media/research.google.com/en/us/pubs/archive/35162.pdf|Bianca Schroeder et al., "DRAM Errors in the Wild: A Large-Scale Field Study", SIGMETRICS 2009.]] | ||
* **[[https://www.cs.princeton.edu/~appel/papers/memerr.pdf|Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", SP 2003.]]** | * **[[https://www.cs.princeton.edu/~appel/papers/memerr.pdf|Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", SP 2003.]]** | ||
+ | * [[https://www.usenix.org/legacy/event/sec08/tech/full_papers/halderman/halderman.pdf|J. Alex Halderman et al., "Lest We Remember: Cold Boot Attacks on Encryption Keys", USENIX Security Symposium 2008.]] | ||
+ | |||
=== 11/12/2014 === | === 11/12/2014 === | ||
Reviews required for both papers, due on Tuesday, Nov 11. | Reviews required for both papers, due on Tuesday, Nov 11. | ||
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* **[[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Maurice Herlihy and J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]]** | * **[[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Maurice Herlihy and J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]]** | ||
* [[http://web.mit.edu/~mmt/Public/Knight86.pdf|Tom Knight, "An achitecture for mostly functional languages", LFP 1986.]] | * [[http://web.mit.edu/~mmt/Public/Knight86.pdf|Tom Knight, "An achitecture for mostly functional languages", LFP 1986.]] | ||
+ | * [[http://www.cs.rice.edu/~alc/old/comp520/papers/SW91.pdf|Frank Schmuck, Jim Wyllie, "Experience with transactions in QuickSilver", SOSP 1991.]] | ||
* [[http://cs.brown.edu/~mph/AspnesH90/p340-aspnes.pdf|James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.]] | * [[http://cs.brown.edu/~mph/AspnesH90/p340-aspnes.pdf|James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.]] | ||
* [[http://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf|Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.]] | * [[http://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf|Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.]] | ||
+ | * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Maurice Herlihy, J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]] | ||
+ | * [[http://csl.stanford.edu/~christos/publications/2006.bliss.taco.pdf|Ahmad Zmily and Christos Kozyrakis, "Block-Aware Instruction Set Architecture", TACO 2006.]] | ||
* [[http://web.stanford.edu/class/cs343/resources/crusoe.pdf|Alexander Klaiber, "The Technology Behind Crusoe™ Processors", 2000.]] | * [[http://web.stanford.edu/class/cs343/resources/crusoe.pdf|Alexander Klaiber, "The Technology Behind Crusoe™ Processors", 2000.]] | ||
* [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | ||
* [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | ||
+ | * [[http://www.christianjacobi.de/publications/jsg12_tx.pdf|Christian Jacobi, et al., "Transactional Memory Architecture and Implementation for IBM System Z", MICRO 2012.]] | ||
* [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=931895|Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.]] | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=931895|Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.]] | ||
* **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** | * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** |