readings
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
readings [2014/11/05 18:32] yixinluo |
readings [2014/11/11 00:20] yixinluo |
||
|---|---|---|---|
| Line 6: | Line 6: | ||
| ==== Reading List (in reverse order) ==== | ==== Reading List (in reverse order) ==== | ||
| + | === 11/13/2014 === | ||
| + | Reviews required for both papers, due on Wednesday, Nov 12. | ||
| + | * **[[http://dl.acm.org/citation.cfm?id=2503257|Sridharan et al., "Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults", SC 2013.]]** | ||
| + | * **[[https://www.cs.princeton.edu/~appel/papers/memerr.pdf|Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", SP 2003.]]** | ||
| + | === 11/12/2014 === | ||
| + | Reviews required for both papers, due on Tuesday, Nov 11. | ||
| + | * **[[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Doe Hyun Yoon, Mattan Erez, "Virtualized and flexible ECC for main memory", ASPLOS 2010.]]** | ||
| + | * **[[http://passat.crhc.illinois.edu/rakeshk/hpca13.pdf|Xun Jian, Rakesh Kumar, "Adaptive Reliability Chipkill Correct (ARCC)", HPCA 2013.]]** | ||
| + | |||
| === 11/5/2014 === | === 11/5/2014 === | ||
| === 10/31/2014 === | === 10/31/2014 === | ||
| Line 16: | Line 25: | ||
| * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | ||
| * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | ||
| + | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=931895|Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.]] | ||
| * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** | * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** | ||
| * [[ftp://ftp.cs.wisc.edu/sohi/papers/1992/isca.esw.pdf|Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.]] | * [[ftp://ftp.cs.wisc.edu/sohi/papers/1992/isca.esw.pdf|Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.]] | ||
| Line 33: | Line 43: | ||
| === 10/16/2014 === | === 10/16/2014 === | ||
| - | Review required (one out of two) due on Wednesday night | + | Consistency II -- Review required (one out of two) due on Wednesday night |
| * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | ||
| * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]] | * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]] | ||
| Line 46: | Line 56: | ||
| * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | ||
| * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | ||
| - | Required review (one out of two) due on Monday night | + | Consistency I -- Required review (one out of two) due on Monday night |
| * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | ||
| * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | ||
| Line 91: | Line 101: | ||
| === 10/1/2014 === | === 10/1/2014 === | ||
| Amirali's literature survey: | Amirali's literature survey: | ||
| + | * FlexRAM | ||
| + | * Active Page | ||
| + | * IRAM | ||
| + | * A Resistive TCAM Accelerator for Data-Intensive Computing | ||
| === 9/30/2014 === | === 9/30/2014 === | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
