readings
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readings [2014/11/05 17:00] yixinluo |
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| * [[http://cs.brown.edu/~mph/AspnesH90/p340-aspnes.pdf|James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.]] | * [[http://cs.brown.edu/~mph/AspnesH90/p340-aspnes.pdf|James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.]] | ||
| * [[http://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf|Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.]] | * [[http://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf|Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.]] | ||
| + | * [[http://web.stanford.edu/class/cs343/resources/crusoe.pdf|Alexander Klaiber, "The Technology Behind Crusoe™ Processors", 2000.]] | ||
| * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]] | ||
| * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]] | ||
| + | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=931895|Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.]] | ||
| * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** | * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]** | ||
| * [[ftp://ftp.cs.wisc.edu/sohi/papers/1992/isca.esw.pdf|Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.]] | * [[ftp://ftp.cs.wisc.edu/sohi/papers/1992/isca.esw.pdf|Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.]] | ||
| * [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/isca.multiscalar.pdf|Sohi et al., “Multiscalar Processors,” ISCA 1995.]] | * [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/isca.multiscalar.pdf|Sohi et al., “Multiscalar Processors,” ISCA 1995.]] | ||
| * [[http://www.cs.cmu.edu/~colohan/papers/tls_isca00.pdf|Steffan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.]] | * [[http://www.cs.cmu.edu/~colohan/papers/tls_isca00.pdf|Steffan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.]] | ||
| + | * [[https://homes.cs.washington.edu/~luisceze/publications/isca06_bulk.pdf|Luis Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.]] | ||
| + | * [[http://www.princeton.edu/~rblee/ELE572Papers/DynamicMultithreadingProc_akkary.pdf?q=tilde/rblee/ELE572Papers/DynamicMultithreadingProc_akkary.pdf|Akkary and Driscoll, “A dynamic multithreading processor,” MICRO 1998.]] | ||
| Required videos for module 2.5.* in [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=schedule#schedule|18-740]]: | Required videos for module 2.5.* in [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=schedule#schedule|18-740]]: | ||
| | 9/25 Wed. | 2.5.1 Speculation | [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pdf|pdf]], [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pptx|pptx]], [[https://www.youtube.com/watch?v=g3IF8DTtr8c|YouTube]][[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=dbb3baf9-c85e-4007-8c71-1e3204fe9907|Panopto]] | [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=readings#module_2-5|readings]] | | | 9/25 Wed. | 2.5.1 Speculation | [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pdf|pdf]], [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pptx|pptx]], [[https://www.youtube.com/watch?v=g3IF8DTtr8c|YouTube]][[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=dbb3baf9-c85e-4007-8c71-1e3204fe9907|Panopto]] | [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=readings#module_2-5|readings]] | | ||
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| === 10/16/2014 === | === 10/16/2014 === | ||
| - | Review required (one out of two) due on Wednesday night | + | Consistency II -- Review required (one out of two) due on Wednesday night |
| * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | ||
| * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]] | * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]] | ||
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| * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | ||
| * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | ||
| - | Required review (one out of two) due on Monday night | + | Consistency I -- Required review (one out of two) due on Monday night |
| * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | ||
| * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | ||
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| === 10/1/2014 === | === 10/1/2014 === | ||
| Amirali's literature survey: | Amirali's literature survey: | ||
| + | * FlexRAM | ||
| + | * Active Page | ||
| + | * IRAM | ||
| + | * A Resistive TCAM Accelerator for Data-Intensive Computing | ||
| === 9/30/2014 === | === 9/30/2014 === | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
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