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readings [2014/10/27 20:58] yixinluo |
readings [2014/11/04 21:26] yixinluo |
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=== 10/14/2014 === | === 10/14/2014 === | ||
- | Background lecture and paper (required reading, no need to review) | + | Background lecture and paper (required reading, no need to review): |
* [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | ||
* [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | ||
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* [[https://cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf|Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.]] | * [[https://cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf|Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.]] | ||
* [[http://research.cs.wisc.edu/multifacet/papers/isca13_direct_segment.pdf|Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.]] | * [[http://research.cs.wisc.edu/multifacet/papers/isca13_direct_segment.pdf|Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.]] | ||
- | Jiyuan's Paper Discussion | + | |
+ | Jiyuan's Paper Discussion: (required 1 out of 3 reviews) | ||
* **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.]]** | * **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.]]** | ||
* [[http://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf|Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.]] | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf|Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.]] | ||
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=== 10/7/2014 === | === 10/7/2014 === | ||
+ | Hui: (required 1 out of 3 reviews) | ||
* **[[http://tinker.cc.gatech.edu/pdfs/MICRO44_Jesse_Beu.pdf|Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.]]** | * **[[http://tinker.cc.gatech.edu/pdfs/MICRO44_Jesse_Beu.pdf|Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.]]** | ||
* **[[http://research.cs.wisc.edu/multifacet/papers/hpca14_quick_release.pdf|Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.]]** | * **[[http://research.cs.wisc.edu/multifacet/papers/hpca14_quick_release.pdf|Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.]]** | ||
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=== 10/2/2014 === | === 10/2/2014 === | ||
+ | Required review for the Memory Forum paper: | ||
^ Due 9/28/2014 | [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | | ^ Due 9/28/2014 | [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | | ||
^ | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ^ | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ||
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=== 9/18/2014 === | === 9/18/2014 === | ||
+ | Yang: (required 1 out of 3 reviews) | ||
* **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | ||
* [[http://users.elis.ugent.be/~leeckhou/papers/isca12-2.pdf|Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.]] | * [[http://users.elis.ugent.be/~leeckhou/papers/isca12-2.pdf|Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.]] | ||
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=== 9/16/2014 === | === 9/16/2014 === | ||
+ | Amirali: (required 1 out of 3 reviews) | ||
* **[[http://users.ece.cmu.edu/~omutlu/pub/rowclone_micro13.pdf|Seshadri et al., "RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data", MICRO 2013.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/rowclone_micro13.pdf|Seshadri et al., "RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data", MICRO 2013.]]** | ||
* [[http://scale.eecs.berkeley.edu/papers/mmp-asplos2002.pdf|Witchel et al., "Mondrian Memory Protection", ASPLOS 2002.]] | * [[http://scale.eecs.berkeley.edu/papers/mmp-asplos2002.pdf|Witchel et al., "Mondrian Memory Protection", ASPLOS 2002.]] | ||
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=== 9/11/2014 === | === 9/11/2014 === | ||
+ | Doru: (required 2 out of 3 reviews) | ||
* **[[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]]** | * **[[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]]** | ||
* [[http://research.cs.wisc.edu/multifacet/papers/tr1593_amdahl_multicore.pdf|Hill et al., "Amdahl’s Law in the Multicore Era", HPCA 2008.]] | * [[http://research.cs.wisc.edu/multifacet/papers/tr1593_amdahl_multicore.pdf|Hill et al., "Amdahl’s Law in the Multicore Era", HPCA 2008.]] | ||
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=== 9/9/2014 === | === 9/9/2014 === | ||
- | Papers discussed in class (and their related papers): | + | Papers discussed in class by Kevin (and their related papers): |
* **[[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]]** | ||
* [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | ||
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=== 8/26/2014 === | === 8/26/2014 === | ||
+ | Required reviews, see three due dates below: | ||
^ Due 9/2/2014 | {{motmoo-springer-chapter-7-30-2014.pdf|Onur Mutlu, "Main Memory Scaling: Challenges and Solution Directions", preprint book Chapter 6, 2014.}} | | ^ Due 9/2/2014 | {{motmoo-springer-chapter-7-30-2014.pdf|Onur Mutlu, "Main Memory Scaling: Challenges and Solution Directions", preprint book Chapter 6, 2014.}} | | ||
^ Due 9/6/2014 | Pick 3 papers referenced by the above paper that pique your interest | | ^ Due 9/6/2014 | Pick 3 papers referenced by the above paper that pique your interest | |