Differences

This shows you the differences between two versions of the page.

--- readings [2014/10/27 20:55]
yixinluo
+++ readings [2014/11/10 22:27]
yixinluo
@@ Line 6: / Line 6: @@
 ==== Reading List (in reverse order) ====
+=== 11/5/2014 ===
 === 10/31/2014 ===
 Review required for the following two papers, due on Friday, Oct 31.
   * **[[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Maurice Herlihy and J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]]**
+    * [[http://web.mit.edu/~mmt/Public/Knight86.pdf|Tom Knight, "An achitecture for mostly functional languages", LFP 1986.]]
+    * [[http://cs.brown.edu/~mph/AspnesH90/p340-aspnes.pdf|James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.]]
+    * [[http://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf|Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.]]
+    * [[http://web.stanford.edu/class/cs343/resources/crusoe.pdf|Alexander Klaiber, "The Technology Behind Crusoe™ Processors", 2000.]]
+    * [[http://courses.cs.vt.edu/cs5204/fall11-kafura/Papers/TransactionalMemory/TM-Book-V2.pdf.pdf|J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).]]
+    * [[http://www.cs.binghamton.edu/~dima/cs580a/spec_wake_micro00.pdf|Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.]]
+    * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=931895|Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.]]
   * **[[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]]**
-Required reading:
+    * [[ftp://ftp.cs.wisc.edu/sohi/papers/1992/isca.esw.pdf|Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.]]
+    * [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/isca.multiscalar.pdf|Sohi et al., “Multiscalar Processors,” ISCA 1995.]]
+    * [[http://www.cs.cmu.edu/~colohan/papers/tls_isca00.pdf|Steffan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.]]
+    * [[https://homes.cs.washington.edu/~luisceze/publications/isca06_bulk.pdf|Luis Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.]]
+    * [[http://www.princeton.edu/~rblee/ELE572Papers/DynamicMultithreadingProc_akkary.pdf?q=tilde/rblee/ELE572Papers/DynamicMultithreadingProc_akkary.pdf|Akkary and Driscoll, “A dynamic multithreading processor,” MICRO 1998.]]
+Required videos for module 2.5.* in [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=schedule#schedule|18-740]]:
 | 9/25 Wed. | 2.5.1 Speculation | [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pdf|pdf]], [[http://www.ece.cmu.edu/~ece742/f14/files/onur-740-fall13-module2.5-speculation.pptx|pptx]], [[https://www.youtube.com/watch?v=g3IF8DTtr8c|YouTube]][[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=dbb3baf9-c85e-4007-8c71-1e3204fe9907|Panopto]] | [[http://www.ece.cmu.edu/~ece740/f13/doku.php?id=readings#module_2-5|readings]] |
 | 9/27 Fri. | 2.5.2 Speculation | [[https://www.youtube.com/watch?v=FqHk4bxrI8Y|video]] [[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=bf92ac2b-5fb5-4896-9bbd-6cb216a16cdd|Panopto]] | ::: |
 | 9/30 Mon. | 2.5.3 Speculation | [[https://www.youtube.com/watch?v=uhyNTy8hvDs|video]] [[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=7dbc66b0-b245-45ba-b047-09a84427676a|Panopto]] | ::: |
 | ::: | 2.5.4 Speculation | [[https://www.youtube.com/watch?v=McMyefc8CCE|video]] [[http://cmu.vid.acatar.com/Panopto/Pages/Viewer/Default.aspx?id=e9eddf7c-c5c0-4ab4-a731-30852d601506|Panopto]] | ::: |
+Related readings:
   * [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/isca.multiscalar.pdf|Sohi et al., “Multiscalar Processors,” ISCA 1995.]]
   * [[http://classes.soe.ucsc.edu/cmpe202/Spring13/papers/12a.pdf|Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005.]]
@@ Line 20: / Line 34: @@
 === 10/16/2014 ===
-Review required (one out of two) due on Wednesday night
+Consistency II -- Review required (one out of two) due on Wednesday night
   * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]**
     * [[http://www.cs.utexas.edu/~pingali/CS395T/2009fa/lectures/herlihy93transactional.pdf|Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.]]
@@ Line 30: / Line 44: @@
 === 10/14/2014 ===
-Background lecture and paper (required reading, no need to review)
+Background lecture and paper (required reading, no need to review):
   * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]]
   * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]]
-Required review (one out of two) due on Monday night
+Consistency I -- Required review (one out of two) due on Monday night
   * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]**
   * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]**
@@ Line 49: / Line 63: @@
   * [[https://cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf|Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.]]
   * [[http://research.cs.wisc.edu/multifacet/papers/isca13_direct_segment.pdf|Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.]]
-Jiyuan's Paper Discussion
+Jiyuan's Paper Discussion: (required 1 out of 3 reviews)
   * **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.]]**
     * [[http://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf|Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.]]
@@ Line 64: / Line 79: @@
 === 10/7/2014 ===
+Hui: (required 1 out of 3 reviews)
   * **[[http://tinker.cc.gatech.edu/pdfs/MICRO44_Jesse_Beu.pdf|Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.]]**
   * **[[http://research.cs.wisc.edu/multifacet/papers/hpca14_quick_release.pdf|Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.]]**
@@ Line 70: / Line 86: @@
 === 10/2/2014 ===
+Required review for the Memory Forum paper:
 ^ Due 9/28/2014 | [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] |
 ^ | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] |
@@ Line 75: / Line 92: @@
 === 10/1/2014 ===
 Amirali's literature survey:
+  * FlexRAM
+  * Active Page
+  * IRAM
+  * A Resistive TCAM Accelerator for Data-Intensive Computing
 === 9/30/2014 ===
@@ Line 126: / Line 147: @@
 === 9/18/2014 ===
+Yang: (required 1 out of 3 reviews)
   * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]**
     * [[http://users.elis.ugent.be/~leeckhou/papers/isca12-2.pdf|Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.]]
@@ Line 140: / Line 162: @@
 === 9/16/2014 ===
+Amirali: (required 1 out of 3 reviews)
   * **[[http://users.ece.cmu.edu/~omutlu/pub/rowclone_micro13.pdf|Seshadri et al., "RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data", MICRO 2013.]]**
     * [[http://scale.eecs.berkeley.edu/papers/mmp-asplos2002.pdf|Witchel et al., "Mondrian Memory Protection", ASPLOS 2002.]]
@@ Line 156: / Line 179: @@
 === 9/11/2014 ===
+Doru: (required 2 out of 3 reviews)
   * **[[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]]**
     * [[http://research.cs.wisc.edu/multifacet/papers/tr1593_amdahl_multicore.pdf|Hill et al., "Amdahl’s Law in the Multicore Era", HPCA 2008.]]
@@ Line 172: / Line 196: @@
 === 9/9/2014 ===
-Papers discussed in class (and their related papers):
+Papers discussed in class by Kevin (and their related papers):
   * **[[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]]**
     * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]]
@@ Line 199: / Line 223: @@
 === 8/26/2014 ===
+Required reviews, see three due dates below:
 ^ Due 9/2/2014 | {{motmoo-springer-chapter-7-30-2014.pdf|Onur Mutlu, "Main Memory Scaling: Challenges and Solution Directions", preprint book Chapter 6, 2014.}} |
 ^ Due 9/6/2014 | Pick 3 papers referenced by the above paper that pique your interest |

18-742 Research in Parallel Computer Architecture, Fall 2014

User Tools

Site Tools

Differences

Page Tools