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* [[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]] | * [[http://www.cs.cmu.edu/~tcm/tcm_papers/isca00.pdf|Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.]] | ||
* **[[https://homes.cs.washington.edu/~luisceze/publications/isca07_bulksc.pdf|Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.]]** | * **[[https://homes.cs.washington.edu/~luisceze/publications/isca07_bulksc.pdf|Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.]]** | ||
+ | * [[https://homes.cs.washington.edu/~luisceze/publications/isca06_bulk.pdf|Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.]] | ||
+ | * [[http://www.ece.cmu.edu/~ece740/f13/lib/exe/fetch.php?media=rajwar01.pdf|Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution”, MICRO 2001.]] | ||
+ | * [[http://www.ece.cmu.edu/~ece740/f13/lib/exe/fetch.php?media=herlihy93.pdf|Herlihy and Moss, “Transactional Memory: Architectural Support for Lock-Free Data Structures”, ISCA 1993.]] | ||
=== 10/14/2014 === | === 10/14/2014 === |