readings
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readings [2014/10/11 19:05] yixinluo |
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| * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | ||
| * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | ||
| + | * [[http://www.csd.uoc.gr/~hy460/pdf/kung.pdf|Kung et al., "On Optimistic Methods for Concurrency Control", TODS 1981.]] | ||
| Recommended book | Recommended book | ||
| * [[http://www.morganclaypool.com/doi/pdfplus/10.2200/S00346ED1V01Y201104CAC016|A Primer on Memory Consistency and Cache Coherence, Chapters 1, 3, 4, 5]] | * [[http://www.morganclaypool.com/doi/pdfplus/10.2200/S00346ED1V01Y201104CAC016|A Primer on Memory Consistency and Cache Coherence, Chapters 1, 3, 4, 5]] | ||
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| * [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | * [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | ||
| * **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | * **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | ||
| + | * [[http://users.ece.gatech.edu/~moin/papers/micro12.pdf|Qureshi et al., "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design", MICRO 2012.]] | ||
| + | * [[http://sampa.cs.washington.edu/papers/micro06_mshr.pdf|Tuck et al., "Scalable Cache Miss Handling for High Memory Level Parallelism", MICRO 2006.]] | ||
| + | * [[http://comparch.gatech.edu/hparch/papers/sim_isca13.pdf|Sim et al., "Resilient die-stacked DRAM caches", ISCA 2013.]] | ||
| * **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | * **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | ||
| + | * [[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CB4QFjAA&url=http%3A%2F%2Fisca2010.inria.fr%2Fmedia%2Fslides%2FISCA_Needle_A_0610.pptx&ei=9kE9VMOuMtLCsATIuIGQCQ&usg=AFQjCNGfI_qA9tHBnR8pJo50uRNYvgVEBw&sig2=OTCWpdAXmMmekm9jun8uBg&bvm=bv.77161500,d.cWc&cad=rja|Dally et al., "Moving the needle Computer Architecture Research in Academe and Industry", ISCA keynote 2010.]] | ||
| === 10/7/2014 === | === 10/7/2014 === | ||
readings.txt ยท Last modified: 2014/12/03 21:12 by yixinluo
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