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readings [2014/10/11 19:05] yixinluo |
readings [2014/10/14 15:10] yixinluo |
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* [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | * [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | ||
* **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | * **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | ||
+ | * [[http://users.ece.gatech.edu/~moin/papers/micro12.pdf|Qureshi et al., "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design", MICRO 2012.]] | ||
+ | * [[http://sampa.cs.washington.edu/papers/micro06_mshr.pdf|Tuck et al., "Scalable Cache Miss Handling for High Memory Level Parallelism", MICRO 2006.]] | ||
+ | * [[http://comparch.gatech.edu/hparch/papers/sim_isca13.pdf|Sim et al., "Resilient die-stacked DRAM caches", ISCA 2013.]] | ||
* **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | * **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | ||