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readings [2014/10/09 14:01] yixinluo |
readings [2014/10/11 19:05] yixinluo |
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==== Reading List (now in reverse order) ==== | ==== Reading List (now in reverse order) ==== | ||
+ | === 10/16/2014 === | ||
+ | Review required (one out of two) due on Wednesday night | ||
+ | * **[[https://homes.cs.washington.edu/~luisceze/publications/isca07_bulksc.pdf|Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.]]** | ||
+ | * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | ||
+ | |||
+ | === 10/14/2014 === | ||
+ | Background lecture and paper (required reading, no need to review) | ||
+ | * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | ||
+ | * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | ||
+ | Required review (one out of two) due on Monday night | ||
+ | * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | ||
+ | * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | ||
+ | Recommended book | ||
+ | * [[http://www.morganclaypool.com/doi/pdfplus/10.2200/S00346ED1V01Y201104CAC016|A Primer on Memory Consistency and Cache Coherence, Chapters 1, 3, 4, 5]] | ||
+ | Further reading in a different area (system level consistency) | ||
+ | * [[http://sns.cs.princeton.edu/docs/eiger-nsdi13.pdf|Lloyd et al., "Stronger Semantics for Low-Latency Geo-Replicated Storage", NSDI 2013.]] | ||
+ | |||
=== 10/9/2014 === | === 10/9/2014 === | ||
- | * **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2013.]]** | + | Amirali's Literature Survey |
+ | * [[http://www.cs.utah.edu/events/thememoryforum/mike.pdf|Connor et al., "Highlights of the high-bandwidth memory (HBM) standard", Memory Forum 2014.]] | ||
+ | * [[https://cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf|Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.]] | ||
+ | * [[http://research.cs.wisc.edu/multifacet/papers/isca13_direct_segment.pdf|Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.]] | ||
+ | Jiyuan's Paper Discussion | ||
+ | * **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.]]** | ||
+ | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf|Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.]] | ||
+ | * [[http://lca.ece.utexas.edu/people/kaseridis/papers/ISCA_2010.pdf]] | ||
+ | * [["FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems"]] | ||
+ | * [[Adaptive History-Based Memory Schedulers]] | ||
+ | * [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | ||
* **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | * **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | ||
+ | * **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | ||
=== 10/7/2014 === | === 10/7/2014 === |