readings
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readings [2014/10/01 15:09] yixinluo |
readings [2014/10/11 18:37] yixinluo |
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| ==== Reading List (now in reverse order) ==== | ==== Reading List (now in reverse order) ==== | ||
| + | === 10/16/2014 === | ||
| + | Review required (one out of two) due on Wednesday night | ||
| + | * **[[https://homes.cs.washington.edu/~luisceze/publications/isca07_bulksc.pdf|Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.]]** | ||
| + | * **[[http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf|Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007]]** | ||
| + | |||
| + | === 10/14/2014 === | ||
| + | Background lecture and paper (required reading, no need to review) | ||
| + | * [[https://www.youtube.com/watch?v=Mq24MXW4g3U|Consistency & Coherence Lecture]] | ||
| + | * [[http://courses.cs.washington.edu/courses/cse548/10wi/Lamport.pdf|Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)]] | ||
| + | Required review (one out of two) due on Monday night | ||
| + | * **[[http://hpc.cs.tsinghua.edu.cn/research/zwm/reading/prof/2a.pdf|Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.]]** | ||
| + | * **[[https://courses.engr.illinois.edu/cs533/sp2012/reading_list/gharachorloo91two.pdf|Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.]]** | ||
| + | |||
| + | === 10/9/2014 === | ||
| + | Amirali's Literature Survey | ||
| + | * [[http://www.cs.utah.edu/events/thememoryforum/mike.pdf|Connor et al., "Highlights of the high-bandwidth memory (HBM) standard", Memory Forum 2014.]] | ||
| + | * [[https://cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf|Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.]] | ||
| + | * [[http://research.cs.wisc.edu/multifacet/papers/isca13_direct_segment.pdf|Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.]] | ||
| + | Jiyuan's Paper Discussion | ||
| + | * **[[http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf|Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.]]** | ||
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf|Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.]] | ||
| + | * [[http://lca.ece.utexas.edu/people/kaseridis/papers/ISCA_2010.pdf]] | ||
| + | * [["FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems"]] | ||
| + | * [[Adaptive History-Based Memory Schedulers]] | ||
| + | * [["Self Optimizing Memory Controllers: A Reinforcement Learning Approach"]] | ||
| + | * **[[http://www.cs.cmu.edu/~chensm/LBA_reading_group/papers/3Ddram-isca08.pdf|Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.]]** | ||
| + | * **[[http://www.dongpingzhang.com/wordpress/wp-content/uploads/2013/06/MSPC6-Zhang.pdf|Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.]]** | ||
| + | |||
| + | === 10/7/2014 === | ||
| + | * **[[http://tinker.cc.gatech.edu/pdfs/MICRO44_Jesse_Beu.pdf|Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.]]** | ||
| + | * **[[http://research.cs.wisc.edu/multifacet/papers/hpca14_quick_release.pdf|Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.]]** | ||
| + | * **[[http://dl.acm.org/citation.cfm?id=2541982|Voskuilen et al., "High-Performance Fractal Coherence", ASPLOS 2014.]]** | ||
| + | |||
| === 10/2/2014 === | === 10/2/2014 === | ||
| Line 12: | Line 45: | ||
| === 10/1/2014 === | === 10/1/2014 === | ||
| - | === 9/30/2014 === | ||
| Amirali's literature survey: | Amirali's literature survey: | ||
| + | === 9/30/2014 === | ||
| Doru's literature survey: | Doru's literature survey: | ||
| * **[[http://users.elis.ugent.be/~leeckhou/papers/isca13.pdf|Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.]]** | * **[[http://users.elis.ugent.be/~leeckhou/papers/isca13.pdf|Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.]]** | ||
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| * [[http://cccp.eecs.umich.edu/papers/lukefahr_micro12.pdf|Andrew Lukefahr et al., "Composite Cores: Pushing Heterogeneity Into a Core", MICRO 2012.]] | * [[http://cccp.eecs.umich.edu/papers/lukefahr_micro12.pdf|Andrew Lukefahr et al., "Composite Cores: Pushing Heterogeneity Into a Core", MICRO 2012.]] | ||
| * [[http://cccp.eecs.umich.edu/papers/shrupad_micro13.pdf|Shruti Padmanabha et al., "Trace based phase prediction for tightly-coupled heterogeneous cores", MICRO 2013.]] | * [[http://cccp.eecs.umich.edu/papers/shrupad_micro13.pdf|Shruti Padmanabha et al., "Trace based phase prediction for tightly-coupled heterogeneous cores", MICRO 2013.]] | ||
| - | * Core-fusion | + | * [[http://m3.csl.cornell.edu/papers/isca07.pdf|Engin Ipek et al., "Core fusion: accommodating software diversity in chip multiprocessors", ISCA 2007.]] |
| - | * Heterogeneous-block architecture | + | * [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-block-architecture_iccd14.pdf|Chris Fallin et al., "The Heterogeneous Block Architecture", ICCD 2014.]] |
| - | * [[http://hps.ece.utexas.edu/pub/TR-HPS-2014-001.pdf]] | + | * [[http://hps.ece.utexas.edu/pub/TR-HPS-2014-001.pdf|Carlos Villavieja et al., "Yoga: A Hybrid Dynamic VLIW/OoO Processor", HPS Tech Report 2014.]] |
| Yang's literature survey: | Yang's literature survey: | ||
| - | * Chao Li, Ruijin Zhou, Tao Li: Enabling distributed generation powered sustainable high-performance data center. HPCA 2013 | + | * [[http://plaza.ufl.edu/chaol/File/Enabling-HPCA-2013.pdf|Chao Li et al., "Enabling distributed generation powered sustainable high-performance data center", HPCA 2013.]] |
| - | * Chao Li, Rui Wang, Tao Li, Depei Qian, Jingling Yuan: Managing Green Datacenters Powered by Hybrid Renewable Energy Systems. ICAC 2014 | + | * [[https://www.usenix.org/system/files/conference/icac14/icac14-paper-li_chao.pdf|Chao Li et al., "Managing Green Datacenters Powered by Hybrid Renewable Energy Systems", ICAC 2014.]] |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6672933&tag=1|Sen Li et al., "Data center power control for frequency regulation", PES 2014.]] | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6672933&tag=1|Sen Li et al., "Data center power control for frequency regulation", PES 2014.]] | ||
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| === 9/24/2014 === | === 9/24/2014 === | ||
| Kevin's literature survey: | Kevin's literature survey: | ||
| - | * **[[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012.]]* | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012.]]** |
| * [[http://arch.ece.gatech.edu/pub/micro40.pdf|Mrinmoy Ghosh et al., "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs", MICRO 2007.]] | * [[http://arch.ece.gatech.edu/pub/micro40.pdf|Mrinmoy Ghosh et al., "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs", MICRO 2007.]] | ||
| * [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | * [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
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