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readings [2014/09/22 19:01] yixinluo |
readings [2014/09/25 17:44] yixinluo |
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==== Reading List (now in reverse order) ==== | ==== Reading List (now in reverse order) ==== | ||
- | === 9/24/2014 === | + | === 10/2/2014 === |
- | Doru's literature survey:\n | + | ^ Due 9/28/2014 | [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | |
+ | ^ | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ||
+ | |||
+ | === 10/1/2014 === | ||
+ | === 9/30/2014 === | ||
+ | Amirali's literature survey: | ||
+ | |||
+ | Doru's literature survey: | ||
* [[http://hps.ece.utexas.edu/pub/morphcore_micro2012.pdf|Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.]] | * [[http://hps.ece.utexas.edu/pub/morphcore_micro2012.pdf|Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.]] | ||
* [[http://users.eecs.northwestern.edu/~rjoseph/eecs453/papers/quereshi-micro2006.pdf|Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.]] | * [[http://users.eecs.northwestern.edu/~rjoseph/eecs453/papers/quereshi-micro2006.pdf|Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.]] | ||
* [[http://users.elis.ugent.be/~leeckhou/papers/isca13.pdf|Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.]] | * [[http://users.elis.ugent.be/~leeckhou/papers/isca13.pdf|Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.]] | ||
+ | Yang's literature survey: | ||
+ | |||
+ | === 9/25/2014 === | ||
+ | * [[http://www.cs.utah.edu/~rajeev/pubs/micro12.pdf|Chatterjee et al., "Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access", MICRO 2012.]] | ||
+ | * [[http://parsa.epfl.ch/cloudsuite/cloudsuite.html|CloudSuite]] | ||
+ | |||
+ | === 9/24/2014 === | ||
+ | Kevin's literature survey: | ||
+ | * [[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012.]] | ||
+ | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-retention-time-characterization_isca13.pdf|Liu et al., "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013.]] | ||
+ | * [[http://www.ece.cmu.edu/~safari/pubs/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf|Khan et al., "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study", SIGMETRICS 2014.]] | ||
+ | |||
+ | === 9/23/2014 === | ||
+ | Hui's literature survey: | ||
+ | * [[https://www.ece.ubc.ca/~aamodt/papers/isingh.hpca2013.pdf|Singh et al., "Cache Coherence for GPU Architectures", HPCA 2013.]] | ||
+ | * [[http://research.cs.wisc.edu/multifacet/papers/micro13_hsc.pdf|Power et al., "Heterogeneous System Coherence for Integrated CPU-GPU Systems", MICRO 2013.]] | ||
+ | * [[http://users.crhc.illinois.edu/djohns53/pub/cohesion-isca2010.pdf|Kelm et al., "Cohesion: A Hybrid Memory Model for Accelerators", ISCA 2010.]] | ||
+ | |||
+ | Jiyuan's literature survey: | ||
+ | * **[[http://cseweb.ucsd.edu/~swanson/papers/ASPLOS2011Prefetching.pdf|Kamruzzaman et al., "Inter-core Prefetching for Multicore Processors Using Migrating Helper Threads", ASPLOS 2011.]]** | ||
+ | * [[http://www.cs.ucf.edu/~zhou/dce_pact_2005_ieee.pdf|Zhou et al., "Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window", PACT 2005.]] | ||
+ | * [[http://people.engr.ncsu.edu/ericro/publications/conference_ASPLOS-9.pdf|Sundaramoorthy et al., "Slipstream Processors: Improving both Performance and Fault Tolerance", ASPLOS 2000.]] | ||
+ | * **[[http://www.cs.utah.edu/wondp/sqrl.pdf|Kumar et al., "SQRL: Hardware Accelerator for Collecting Software Data Structures", PACT 2014.]]** | ||
+ | * **[[http://www.cse.ust.hk/catalac/papers/scatter_sc07.pdf|He et al., "Efficient Gather and Scatter Operations on Graphics Processors", SC 2007.]]** | ||
+ | * [[http://www.cs.utah.edu/~ald/pubs/hpca99.pdf|Carter et al., "Impulse: Building a Smarter Memory Controller", HPCA 1999.]] | ||
+ | * [[http://www.cs.utah.edu/~rajeev/pubs/asplos10.pdf|Sudan et al., "Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement", ASPLOS 2010.]] | ||
=== 9/18/2014 === | === 9/18/2014 === |