readings
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| * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | ||
| + | * [[http://users.elis.ugent.be/~leeckhou/papers/isca12-2.pdf|Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.]] | ||
| + | * [[http://mprc.pku.edu.cn/~liuxianhua/chn/corpus/Notes/articles/isca/ISCA2002/p47.pdf|Fields et al., "Slack: Maximizing Performance Under Technological Constraints", ISCA 2002.]] | ||
| + | * [[http://cadal3.cse.nsysu.edu.tw/seminar/seminar_file/2002/10/Focusing%20processor%20policies%20via%20critical-path%20prediction.pdf|Fields et al., "Focusing Processor Policies via Critical-Path Prediction", ISCA 2001.]] | ||
| + | * [[http://www.ece.ncsu.edu/arpers/Papers/faircaching.pdf|Kim et al., "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture", PACT 2004.]] | ||
| * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | ||
| + | * [[http://cseweb.ucsd.edu/~calder/papers/ASPLOS-02-SimPoint.pdf|Sherwood et al., "Automatically characterizing large scale program behavior", ASPLOS 2002.]] | ||
| + | * [[http://cseweb.ucsd.edu/~calder/papers/ISCA-03-Phase.pdf|Sherwood et al., "Phase Tracking and Prediction", ISCA 2003.]] | ||
| + | * [[http://www.csl.cornell.edu/~martinez/doc/isca13-ghose.pdf|Ghose et al., "Improving memory scheduling via processor-side load criticality information", ISCA 2013.]] | ||
| + | * [[http://users.eecs.northwestern.edu/~rjoseph/eecs453/papers/quereshi-micro2006.pdf|Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.]] | ||
| + | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=165388|Stone et al., "Optimal partitioning of cache memory", IEEE Trans. 1992.]] | ||
| * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | ||
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