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readings [2014/09/17 00:56] yixinluo |
readings [2014/09/25 17:44] yixinluo |
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| ==== Reading List (now in reverse order) ==== | ==== Reading List (now in reverse order) ==== | ||
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| + | === 10/2/2014 === | ||
| + | ^ Due 9/28/2014 | [[http://www.cs.utah.edu/events/thememoryforum/kang.pdf|Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.]] | | ||
| + | ^ | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ||
| + | |||
| + | === 10/1/2014 === | ||
| + | === 9/30/2014 === | ||
| + | Amirali's literature survey: | ||
| + | |||
| + | Doru's literature survey: | ||
| + | * [[http://hps.ece.utexas.edu/pub/morphcore_micro2012.pdf|Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.]] | ||
| + | * [[http://users.eecs.northwestern.edu/~rjoseph/eecs453/papers/quereshi-micro2006.pdf|Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.]] | ||
| + | * [[http://users.elis.ugent.be/~leeckhou/papers/isca13.pdf|Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.]] | ||
| + | Yang's literature survey: | ||
| + | |||
| + | === 9/25/2014 === | ||
| + | * [[http://www.cs.utah.edu/~rajeev/pubs/micro12.pdf|Chatterjee et al., "Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access", MICRO 2012.]] | ||
| + | * [[http://parsa.epfl.ch/cloudsuite/cloudsuite.html|CloudSuite]] | ||
| + | |||
| + | === 9/24/2014 === | ||
| + | Kevin's literature survey: | ||
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012.]] | ||
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-retention-time-characterization_isca13.pdf|Liu et al., "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013.]] | ||
| + | * [[http://www.ece.cmu.edu/~safari/pubs/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf|Khan et al., "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study", SIGMETRICS 2014.]] | ||
| + | |||
| + | === 9/23/2014 === | ||
| + | Hui's literature survey: | ||
| + | * [[https://www.ece.ubc.ca/~aamodt/papers/isingh.hpca2013.pdf|Singh et al., "Cache Coherence for GPU Architectures", HPCA 2013.]] | ||
| + | * [[http://research.cs.wisc.edu/multifacet/papers/micro13_hsc.pdf|Power et al., "Heterogeneous System Coherence for Integrated CPU-GPU Systems", MICRO 2013.]] | ||
| + | * [[http://users.crhc.illinois.edu/djohns53/pub/cohesion-isca2010.pdf|Kelm et al., "Cohesion: A Hybrid Memory Model for Accelerators", ISCA 2010.]] | ||
| + | |||
| + | Jiyuan's literature survey: | ||
| + | * **[[http://cseweb.ucsd.edu/~swanson/papers/ASPLOS2011Prefetching.pdf|Kamruzzaman et al., "Inter-core Prefetching for Multicore Processors Using Migrating Helper Threads", ASPLOS 2011.]]** | ||
| + | * [[http://www.cs.ucf.edu/~zhou/dce_pact_2005_ieee.pdf|Zhou et al., "Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window", PACT 2005.]] | ||
| + | * [[http://people.engr.ncsu.edu/ericro/publications/conference_ASPLOS-9.pdf|Sundaramoorthy et al., "Slipstream Processors: Improving both Performance and Fault Tolerance", ASPLOS 2000.]] | ||
| + | * **[[http://www.cs.utah.edu/wondp/sqrl.pdf|Kumar et al., "SQRL: Hardware Accelerator for Collecting Software Data Structures", PACT 2014.]]** | ||
| + | * **[[http://www.cse.ust.hk/catalac/papers/scatter_sc07.pdf|He et al., "Efficient Gather and Scatter Operations on Graphics Processors", SC 2007.]]** | ||
| + | * [[http://www.cs.utah.edu/~ald/pubs/hpca99.pdf|Carter et al., "Impulse: Building a Smarter Memory Controller", HPCA 1999.]] | ||
| + | * [[http://www.cs.utah.edu/~rajeev/pubs/asplos10.pdf|Sudan et al., "Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement", ASPLOS 2010.]] | ||
| === 9/18/2014 === | === 9/18/2014 === | ||
| * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | ||
| - | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | + | * [[http://users.elis.ugent.be/~leeckhou/papers/isca12-2.pdf|Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.]] |
| + | * [[http://mprc.pku.edu.cn/~liuxianhua/chn/corpus/Notes/articles/isca/ISCA2002/p47.pdf|Fields et al., "Slack: Maximizing Performance Under Technological Constraints", ISCA 2002.]] | ||
| + | * [[http://cadal3.cse.nsysu.edu.tw/seminar/seminar_file/2002/10/Focusing%20processor%20policies%20via%20critical-path%20prediction.pdf|Fields et al., "Focusing Processor Policies via Critical-Path Prediction", ISCA 2001.]] | ||
| + | * [[http://www.ece.ncsu.edu/arpers/Papers/faircaching.pdf|Kim et al., "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture", PACT 2004.]] | ||
| * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | ||
| + | * [[http://cseweb.ucsd.edu/~calder/papers/ASPLOS-02-SimPoint.pdf|Sherwood et al., "Automatically characterizing large scale program behavior", ASPLOS 2002.]] | ||
| + | * [[http://cseweb.ucsd.edu/~calder/papers/ISCA-03-Phase.pdf|Sherwood et al., "Phase Tracking and Prediction", ISCA 2003.]] | ||
| + | * [[http://www.csl.cornell.edu/~martinez/doc/isca13-ghose.pdf|Ghose et al., "Improving memory scheduling via processor-side load criticality information", ISCA 2013.]] | ||
| + | * [[http://users.eecs.northwestern.edu/~rjoseph/eecs453/papers/quereshi-micro2006.pdf|Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.]] | ||
| + | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=165388|Stone et al., "Optimal partitioning of cache memory", IEEE Trans. 1992.]] | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | ||
| === 9/16/2014 === | === 9/16/2014 === | ||
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| * [[http://www.ai.mit.edu/projects/aries/course/notes/terasys.pdf|Gokhale et al., "Processing in memory: The Terasys massively parallel PIM array." Computer 28.4 1995.]] | * [[http://www.ai.mit.edu/projects/aries/course/notes/terasys.pdf|Gokhale et al., "Processing in memory: The Terasys massively parallel PIM array." Computer 28.4 1995.]] | ||
| * [[http://www.eecg.toronto.edu/~dunc/cram/#Bibliography|The Computational RAM (C-RAM) project.]] | * [[http://www.eecg.toronto.edu/~dunc/cram/#Bibliography|The Computational RAM (C-RAM) project.]] | ||
| + | * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | ||
| * **[[http://users.ece.cmu.edu/~omutlu/pub/bdi-compression_pact12.pdf|Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/bdi-compression_pact12.pdf|Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.]]** | ||
| + | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6657054|Chen et al., "Free ECC: An efficient error protection for compressed last-level caches", ICCD 2013.]] | ||
| + | * [[http://taco.cse.tamu.edu/pdfs/p53-tian.pdf|Tian et al., "Last-Level Cache Deduplication", ICS 2014.]] | ||
| + | * [[http://dl.acm.org/citation.cfm?id=2370864|Sathish et al., "Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads", PACT 2012.]] | ||
| * **[[http://users.ece.cmu.edu/~omutlu/pub/linearly-compressed-pages_micro13.pdf|Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/linearly-compressed-pages_micro13.pdf|Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.]]** | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
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