This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
readings [2014/09/17 00:56] yixinluo |
readings [2014/09/18 15:42] yixinluo |
||
---|---|---|---|
Line 9: | Line 9: | ||
=== 9/18/2014 === | === 9/18/2014 === | ||
* **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | ||
- | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | ||
* **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | ||
+ | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | ||
=== 9/16/2014 === | === 9/16/2014 === | ||
Line 21: | Line 21: | ||
* [[http://www.ai.mit.edu/projects/aries/course/notes/terasys.pdf|Gokhale et al., "Processing in memory: The Terasys massively parallel PIM array." Computer 28.4 1995.]] | * [[http://www.ai.mit.edu/projects/aries/course/notes/terasys.pdf|Gokhale et al., "Processing in memory: The Terasys massively parallel PIM array." Computer 28.4 1995.]] | ||
* [[http://www.eecg.toronto.edu/~dunc/cram/#Bibliography|The Computational RAM (C-RAM) project.]] | * [[http://www.eecg.toronto.edu/~dunc/cram/#Bibliography|The Computational RAM (C-RAM) project.]] | ||
+ | * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | ||
* **[[http://users.ece.cmu.edu/~omutlu/pub/bdi-compression_pact12.pdf|Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/bdi-compression_pact12.pdf|Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.]]** | ||
+ | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6657054|Chen et al., "Free ECC: An efficient error protection for compressed last-level caches", ICCD 2013.]] | ||
+ | * [[http://taco.cse.tamu.edu/pdfs/p53-tian.pdf|Tian et al., "Last-Level Cache Deduplication", ICS 2014.]] | ||
+ | * [[http://dl.acm.org/citation.cfm?id=2370864|Sathish et al., "Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads", PACT 2012.]] | ||
* **[[http://users.ece.cmu.edu/~omutlu/pub/linearly-compressed-pages_micro13.pdf|Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/linearly-compressed-pages_micro13.pdf|Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.]]** | ||