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readings [2014/09/10 00:48] yixinluo |
readings [2014/09/11 15:10] yixinluo |
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=== 9/11/2014 === | === 9/11/2014 === | ||
- | * [[http://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf|Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems", HPCA 2013.]] | ||
* [[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]] | * [[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]] | ||
* [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf|Joao et al., "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012.]] | * [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf|Joao et al., "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012.]] | ||
+ | * [[http://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf|Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems", HPCA 2013.]] | ||
+ | |||
+ | === 9/16/2014 === | ||
+ | * Base-Delta-Immediate Compression | ||
+ | * RowClone | ||
+ | * more is coming | ||
+ | |||
+ | === 9/18/2014 === | ||
+ | * stall-time fair memory access scheduling for chip multiprocessors | ||
+ | * fairness via source throttling | ||
+ | * Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling, Sigmetrics 2012. |