readings
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| * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | ||
| * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | ||
| + | * [[http://cfall.in/pubs/micro2011_pams.pdf|Fallin et al., "Parallel Application Memory Scheduling", MICRO 2011.]] | ||
| * **[[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]]** | * **[[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]]** | ||
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