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readings [2014/09/09 18:01] yixinluo |
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| | | [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|Jones, "How to Write a Great Research Paper".]] | | | | [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|Jones, "How to Write a Great Research Paper".]] | | ||
| | | [[http://www2.cs.uregina.ca/~pwlfong/CS499/writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”, 2004.]] | | | | [[http://www2.cs.uregina.ca/~pwlfong/CS499/writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”, 2004.]] | | ||
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| === 9/3/2014 === | === 9/3/2014 === | ||
| | DRAM arch. | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | | DRAM arch. | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ||
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| | In mem comp. | [[http://www.ece.umd.edu/courses/enee759m.S2002/papers/fromm1997-isca24.pdf|Fromm et al., "The Energy Efficiency of IRAM Architectures", ISCA 1997.]] | | | In mem comp. | [[http://www.ece.umd.edu/courses/enee759m.S2002/papers/fromm1997-isca24.pdf|Fromm et al., "The Energy Efficiency of IRAM Architectures", ISCA 1997.]] | | ||
| | In mem comp. | [[http://www.eecs.berkeley.edu/~yelick/yelick/iram-micro97.pdf|Patterson et al., "A Case for Intelligent DRAM: IRAM", IEEE Micro 1997.]] | | | In mem comp. | [[http://www.eecs.berkeley.edu/~yelick/yelick/iram-micro97.pdf|Patterson et al., "A Case for Intelligent DRAM: IRAM", IEEE Micro 1997.]] | | ||
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| === 9/9/2014 === | === 9/9/2014 === | ||
| Papers discussed in class (and their related papers): | Papers discussed in class (and their related papers): | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]]** |
| * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | ||
| * [[https://www.cs.sfu.ca/~ashriram/publications/2012_MICRO_AmoebaCache.pdf|Kumar et al., "Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy", MICRO 2012.]] | * [[https://www.cs.sfu.ca/~ashriram/publications/2012_MICRO_AmoebaCache.pdf|Kumar et al., "Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy", MICRO 2012.]] | ||
| * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/staged-memory-scheduling_isca12.pdf|Ausavarungnirun et al., "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems", ISCA 2012.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/staged-memory-scheduling_isca12.pdf|Ausavarungnirun et al., "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems", ISCA 2012.]]** |
| * [[https://www.usenix.org/legacy/publications/library/proceedings/osdi/full_papers/waldspurger.pdf|Waldspurger et al., "Lottery Scheduling: Flexible Proportional-Share Resource Management", OSDI 1994.]] | * [[https://www.usenix.org/legacy/publications/library/proceedings/osdi/full_papers/waldspurger.pdf|Waldspurger et al., "Lottery Scheduling: Flexible Proportional-Share Resource Management", OSDI 1994.]] | ||
| * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | ||
| * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]] | + | * [[http://cfall.in/pubs/micro2011_pams.pdf|Fallin et al., "Parallel Application Memory Scheduling", MICRO 2011.]] |
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]]** | ||
| === 9/11/2014 === | === 9/11/2014 === | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf|Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems", HPCA 2013.]] | + | * **[[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]]** |
| - | * [[http://users.elis.ugent.be/~seyerman/ISCA10.pdf|Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.]] | + | * [[http://research.cs.wisc.edu/multifacet/papers/tr1593_amdahl_multicore.pdf|Hill et al., "Amdahl’s Law in the Multicore Era", HPCA 2008.]] |
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf|Joao et al., "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf|Joao et al., "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012.]]** |
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf|Suleman et al., "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures", ASPLOS 2009.]] | ||
| + | * [[http://www.ann.ece.ufl.edu/courses/eel6686_14spr/papers/MeetingPointsUsingThreadCriticalitytToAdaptToMulticoreHardwareToParallelRegions.pdf|Cai et al., "Meeting Points: Using Thread Criticality to Adapt Multicore Hardware to Parallel Regions", PACT 2008.]] | ||
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/srinath_hpca07.pdf|Srinath et al., "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers", HPCA 2007.]] | ||
| + | * [[http://mrmgroup.cs.princeton.edu/papers/abhattac-isca2009.pdf|Bhattacharjee et al., "Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors", ISCA 2009.]] | ||
| + | * [[http://users.ece.cmu.edu/~omutlu/pub/dm_isca10.pdf|Suleman et al., "Data Marshaling for Multi-core Systems", ISCA 2010.]] | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf|Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems", HPCA 2013.]]** | ||
| + | * [[http://hps.ece.utexas.edu/pub/morphcore_micro2012.pdf|Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.]] | ||
| + | * [[http://m3.csl.cornell.edu/papers/isca07.pdf|Ipek et al., "Core Fusion: Accommodating Software Diversity in Chip Multiprocessors", ISCA 2007.]] | ||
| + | * [[http://www.istc-cc.cmu.edu/publications/papers/2013/joao_isca13_preprint.pdf|Joao et al., "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs", ISCA 2013.]] | ||
| + | * [[http://cseweb.ucsd.edu/~calder/papers/ISCA-03-Phase.pdf|Sherwood et al., "Phase Tracking and Prediction", ISCA 2003.]] | ||
| + | * [[http://www.cs.rochester.edu/~ipek/micro08.pdf|Bitirgen et al., "Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach", MICRO 2008.]] | ||
| + | |||
| + | === 9/16/2014 === | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/bdi-compression_pact12.pdf|Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.]]** | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/rowclone_micro13.pdf|Seshadri et al., "RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data", MICRO 2013.]]** | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/linearly-compressed-pages_micro13.pdf|Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.]]** | ||
| + | |||
| + | === 9/18/2014 === | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/stfm_micro07.pdf|Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.]]** | ||
| + | * **[[http://users.ece.cmu.edu/~omutlu/pub/fairness-via-throttling_acm_tocs12.pdf|Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.]]** | ||
| + | * **[[ftp://ftp-sop.inria.fr/maestro/Sigmetrics-Performance-2012-papers-and-posters/p295.pdf|Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.]]** | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
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