readings
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
readings [2014/09/09 18:01] yixinluo |
readings [2014/09/09 23:55] yixinluo |
||
|---|---|---|---|
| Line 17: | Line 17: | ||
| | | [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|Jones, "How to Write a Great Research Paper".]] | | | | [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|Jones, "How to Write a Great Research Paper".]] | | ||
| | | [[http://www2.cs.uregina.ca/~pwlfong/CS499/writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”, 2004.]] | | | | [[http://www2.cs.uregina.ca/~pwlfong/CS499/writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”, 2004.]] | | ||
| + | |||
| === 9/3/2014 === | === 9/3/2014 === | ||
| | DRAM arch. | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | | DRAM arch. | [[http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | | ||
| Line 30: | Line 31: | ||
| | In mem comp. | [[http://www.ece.umd.edu/courses/enee759m.S2002/papers/fromm1997-isca24.pdf|Fromm et al., "The Energy Efficiency of IRAM Architectures", ISCA 1997.]] | | | In mem comp. | [[http://www.ece.umd.edu/courses/enee759m.S2002/papers/fromm1997-isca24.pdf|Fromm et al., "The Energy Efficiency of IRAM Architectures", ISCA 1997.]] | | ||
| | In mem comp. | [[http://www.eecs.berkeley.edu/~yelick/yelick/iram-micro97.pdf|Patterson et al., "A Case for Intelligent DRAM: IRAM", IEEE Micro 1997.]] | | | In mem comp. | [[http://www.eecs.berkeley.edu/~yelick/yelick/iram-micro97.pdf|Patterson et al., "A Case for Intelligent DRAM: IRAM", IEEE Micro 1997.]] | | ||
| + | |||
| === 9/9/2014 === | === 9/9/2014 === | ||
| Papers discussed in class (and their related papers): | Papers discussed in class (and their related papers): | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index", ISCA 2014.]]** |
| * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | * [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf|Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.]] | ||
| * [[https://www.cs.sfu.ca/~ashriram/publications/2012_MICRO_AmoebaCache.pdf|Kumar et al., "Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy", MICRO 2012.]] | * [[https://www.cs.sfu.ca/~ashriram/publications/2012_MICRO_AmoebaCache.pdf|Kumar et al., "Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy", MICRO 2012.]] | ||
| * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | * [[http://pages.cs.wisc.edu/~isca2005/papers/04B-03.PDF|Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.]] | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/staged-memory-scheduling_isca12.pdf|Ausavarungnirun et al., "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems", ISCA 2012.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/staged-memory-scheduling_isca12.pdf|Ausavarungnirun et al., "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems", ISCA 2012.]]** |
| * [[https://www.usenix.org/legacy/publications/library/proceedings/osdi/full_papers/waldspurger.pdf|Waldspurger et al., "Lottery Scheduling: Flexible Proportional-Share Resource Management", OSDI 1994.]] | * [[https://www.usenix.org/legacy/publications/library/proceedings/osdi/full_papers/waldspurger.pdf|Waldspurger et al., "Lottery Scheduling: Flexible Proportional-Share Resource Management", OSDI 1994.]] | ||
| * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | * [[http://www.eecg.toronto.edu/~moshovos/ACA05/read/complexity.pdf|Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.]] | ||
| * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | * [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.]] | ||
| - | * [[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]] | + | * **[[http://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.]]** |
| === 9/11/2014 === | === 9/11/2014 === | ||
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
