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readings [2014/09/03 15:58]
yixinluo
readings [2014/09/09 23:55]
yixinluo
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 === 8/26/2014 === === 8/26/2014 ===
 ^ Due 9/2/2014 | {{motmoo-springer-chapter-7-30-2014.pdf|Onur Mutlu, "Main Memory Scaling: Challenges and Solution Directions",​ preprint book Chapter 6, 2014.}} | ^ Due 9/2/2014 | {{motmoo-springer-chapter-7-30-2014.pdf|Onur Mutlu, "Main Memory Scaling: Challenges and Solution Directions",​ preprint book Chapter 6, 2014.}} |
-^ Due 9/4/2014 | Pick 3 papers referenced by the above paper that pique your interest |+^ Due 9/6/2014 | Pick 3 papers referenced by the above paper that pique your interest |
 ^ Due 9/6/2014 | [[http://​www.cs.virginia.edu/​~robins/​YouAndYourResearch.html|Hamming,​ "You and Your Research,"​ Bell Communications Research Colloquium Seminar, 7 March 1986.]] | ^ Due 9/6/2014 | [[http://​www.cs.virginia.edu/​~robins/​YouAndYourResearch.html|Hamming,​ "You and Your Research,"​ Bell Communications Research Colloquium Seminar, 7 March 1986.]] |
 | | [[http://​web.stanford.edu/​class/​cs240/​readings/​lampson-hints.pdf|Butler W. Lampson, "Hints for computer system design",​ SOSP 1983]] | | | [[http://​web.stanford.edu/​class/​cs240/​readings/​lampson-hints.pdf|Butler W. Lampson, "Hints for computer system design",​ SOSP 1983]] |
Line 17: Line 17:
 | | [[http://​research.microsoft.com/​en-us/​um/​people/​simonpj/​papers/​giving-a-talk/​writing-a-paper-slides.pdf|Jones,​ "How to Write a Great Research Paper"​.]] | | | [[http://​research.microsoft.com/​en-us/​um/​people/​simonpj/​papers/​giving-a-talk/​writing-a-paper-slides.pdf|Jones,​ "How to Write a Great Research Paper"​.]] |
 | | [[http://​www2.cs.uregina.ca/​~pwlfong/​CS499/​writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”,​ 2004.]] | | | [[http://​www2.cs.uregina.ca/​~pwlfong/​CS499/​writing-paper.pdf|Philip W. L. Fong, “How to Write a CS Research Paper: A Bibliography”,​ 2004.]] |
 +
 === 9/3/2014 === === 9/3/2014 ===
-| | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | +DRAM arch. | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​salp-dram_isca12.pdf|Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM", ISCA 2012.]] | 
-| | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​raidr-dram-refresh_isca12.pdf|Liu et al., "​RAIDR:​ Retention-Aware Intelligent DRAM Refresh",​ ISCA 2012.]] | +DRAM arch. | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​raidr-dram-refresh_isca12.pdf|Liu et al., "​RAIDR:​ Retention-Aware Intelligent DRAM Refresh",​ ISCA 2012.]] | 
-| | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​flash-error-analysis-and-management_itj13.pdf|Cai et al, "Error Analysis and Retention-Aware Error Management for NAND Flash Memory",​ ITJ Vol. 17-1 2013]] | +Flash | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​flash-error-analysis-and-management_itj13.pdf|Cai et al., "Error Analysis and Retention-Aware Error Management for NAND Flash Memory",​ ITJ Vol. 17-1 2013.]] | 
-| | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf|Khan et al, "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study",​ SIGMETRICS 2014]] |+DRAM reliab. ​| [[http://​users.ece.cmu.edu/​~omutlu/​pub/​error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf|Khan et al., "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study",​ SIGMETRICS 2014.]] | 
 +| Reliability | [[http://​www.crhc.illinois.edu/​ACS/​pub/​branchflip.pdf|Wang et al., "​Y-Branches:​ When You Come to a Fork in the Road, Take It", PACT 2003.]] | 
 +| Reliability | [[http://​users.ece.cmu.edu/​~omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Luo et al., "​Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost", DSN 2014.]] | 
 +| Security | [[https://​www.cs.princeton.edu/​~appel/​papers/​memerr.pdf|Govindavajhala et al., "Using Memory Errors to Attack a Virtual Machine",​ SP 2003.]] | 
 +| 3d stacking | [[http://​www.cs.cmu.edu/​~chensm/​LBA_reading_group/​papers/​3Ddram-isca08.pdf|Loh et al., "​3D-Stacked Memory Architectures for Multi-core Processors",​ ISCA 2008.]] | 
 +| 3d stacking | [[http://​pdf.aminer.org/​000/​499/​580/​die_stacking_d_microarchitecture.pdf|Black et al., "Die Stacking (3D) Microarchitecture",​ MICRO 2006.]] | 
 +| In mem comp. | [[http://​ieeexplore.ieee.org/​stamp/​stamp.jsp?​arnumber=4115697|Kogge et al., "​EXECUBE - A New Architecture for Scalable MPPs", ICPP 1994.]] | 
 +| In mem comp. | [[http://​www.ece.umd.edu/​courses/​enee759m.S2002/​papers/​fromm1997-isca24.pdf|Fromm et al., "The Energy Efficiency of IRAM Architectures",​ ISCA 1997.]] | 
 +| In mem comp. | [[http://​www.eecs.berkeley.edu/​~yelick/​yelick/​iram-micro97.pdf|Patterson et al., "A Case for Intelligent DRAM: IRAM", IEEE Micro 1997.]] | 
 + 
 +=== 9/9/2014 === 
 +Papers discussed in class (and their related papers): 
 +  * **[[http://​users.ece.cmu.edu/​~omutlu/​pub/​dirty-block-index_isca14.pdf|Seshadri et al., "The Dirty-Block Index",​ ISCA 2014.]]** 
 +    * [[http://​users.ece.utexas.edu/​~merez/​vecc_asplos_2010.pdf|Yoon et al., "​Virtualized and Flexible ECC for Main Memory",​ ASPLOS 2010.]] 
 +    * [[https://​www.cs.sfu.ca/​~ashriram/​publications/​2012_MICRO_AmoebaCache.pdf|Kumar et al., "​Amoeba-Cache:​ Adaptive Blocks for Eliminating Waste in the Memory Hierarchy",​ MICRO 2012.]] 
 +    * [[http://​pages.cs.wisc.edu/​~isca2005/​papers/​04B-03.PDF|Cantin et al., "​Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking",​ ISCA 2005.]] 
 +  * **[[http://​users.ece.cmu.edu/​~omutlu/​pub/​staged-memory-scheduling_isca12.pdf|Ausavarungnirun et al., "​Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems",​ ISCA 2012.]]** 
 +    * [[https://​www.usenix.org/​legacy/​publications/​library/​proceedings/​osdi/​full_papers/​waldspurger.pdf|Waldspurger et al., "​Lottery Scheduling: Flexible Proportional-Share Resource Management",​ OSDI 1994.]] 
 +    * [[http://​www.eecg.toronto.edu/​~moshovos/​ACA05/​read/​complexity.pdf|Palacharla et al., "​Complexity-Effective Superscalar Processors",​ ISCA 1997.]] 
 +    * [[http://​users.ece.cmu.edu/​~omutlu/​pub/​parbs_isca08.pdf|Mutlu et al., "​Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers",​ ISCA 2008.]] 
 +  * **[[http://​users.ece.cmu.edu/​~omutlu/​pub/​dram-access-refresh-parallelization_hpca14.pdf|Chang et al., "​Improving DRAM Performance by Parallelizing Refreshes with Accesses",​ HPCA 2014.]]** 
 + 
 +=== 9/11/2014 === 
 +  * [[http://​users.ece.cmu.edu/​~omutlu/​pub/​mise-predictable_memory_performance-hpca13.pdf|Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems",​ HPCA 2013.]] 
 +  * [[http://​users.elis.ugent.be/​~seyerman/​ISCA10.pdf|Eyerman et al., "​Modeling critical sections in amdahl’s law and its implications for multicore design",​ ISCA 2010.]] 
 +  * [[http://​users.ece.cmu.edu/​~omutlu/​pub/​bottleneck-identification-and-scheduling_asplos12.pdf|Joao et al., "​Bottleneck Identification and Scheduling in Multithreaded Applications",​ ASPLOS 2012.]]
readings.txt · Last modified: 2014/12/03 21:12 by yixinluo