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reviews [2012/09/07 18:55]
hanbiny
reviews [2014/09/02 03:31] (current)
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 =====Paper Reviews===== =====Paper Reviews=====
- 
 Post your reviews of the assigned papers on the [[http://sourcery.cmcl.cs.cmu.edu:4000/collections/show/48|Paper Review Board]]. Post your reviews of the assigned papers on the [[http://sourcery.cmcl.cs.cmu.edu:4000/collections/show/48|Paper Review Board]].
  
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   * Near the bottom of the page, click 'add review'.   * Near the bottom of the page, click 'add review'.
  
-=====Lecture 1=====+=====Lecture 1=====
-{{anchor:L1}} +
   * Due Sep 11th - Pick two papers from [[http://isca2012.ittc.ku.edu/index.php?option=com_content&view=article&id=53&Itemid=57|ISCA 2012 proceedings]].   * Due Sep 11th - Pick two papers from [[http://isca2012.ittc.ku.edu/index.php?option=com_content&view=article&id=53&Itemid=57|ISCA 2012 proceedings]].
     * At least one of them should be new to you.     * At least one of them should be new to you.
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     * Monday, September 10, 2012 7-9 pm, HH-1107.     * Monday, September 10, 2012 7-9 pm, HH-1107.
  
 +=====Lecture 2=====
 +  * Due Sep 16th - Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,” ASPLOS 2009. {{:suleman09-acs.pdf|pdf}}
 +  * Due Sep 16th - Suleman et al., “Data Marshaling for Multi-core Architectures,” ISCA 2010. {{:suleman_marshaling.pdf|pdf}}
 +  * Due Sep 16th - Joao et al., “Bottleneck Identification and Scheduling in Multithreaded Applications,” ASPLOS 2012. {{:joao12-bottleneck.pdf|pdf}}
 +
 +=====Lecture 5=====
 +  * Due Sep 21st - Smith, "Architecture and applications of the HEP multiprocessor computer system," SPIE 1981. {{:smith81-hep.pdf|pdf}}
 +  * Due Sep 21st - Tullsen et al., "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor," ISCA 1996. {{:tullsen96_smt.pdf|pdf}}
 +  * Due Sep 21st - Chappell et al., "Simultaneous Subordinate Microthreading (SSMT)," ISCA 1999. {{:chappell_ssmt99.pdf|pdf}}
 +  * Due Sep 21st - Reinhardt and Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," ISCA 2000. {{:reinhardt_faultdetectsmt00.pdf|pdf}}
 +
 +=====Lecture 8=====
 +  * Due Sep 30th - Onur Mutlu, "Some Ideas and Principles for Achieving Higher System Energy Efficiency," NSF Position Paper and Presentation 2012. {{:mutlu_criticality-based-resource-management_nsf-cpom12.pdf|pdf}}
 +  * Due Sep 30th - Ebrahimi et al., "Parallel Application Memory Scheduling," MICRO 2011. {{:ebrahimi11-parallel.pdf|pdf}}
 +  * Due Sep 30th - Seshadri et al., "The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing," PACT 2012. {{:seshadri12-eaf.pdf|pdf}}
 +  * Due Sep 30th - Pekhimenko et al., "Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency," CMU SAFARI Technical Report 2012. {{:pekhimenko12tr-compressed.pdf|pdf}}
 +
 +=====Lecture 13=====
 +  * Due Oct 9th - Sohi et al., "Multiscalar processors," ISCA 1995. {{:sohi95.pdf|pdf}}
 +  * Due Oct 9th - CALCM Seminar: Scale-Out Processors.
 +    * CALCM Seminar by Boris Grot (EPFL).
 +    * Monday, October 8, 2012 10-11 am, CIC 4th floor ISTC - Panther Hollow Room.
 +
 +  * Due Oct 11th - Herlihy and Moss, "Transactional memory: architectural support for lock-free data structures," ISCA 1993. {{:herlihy93.pdf|pdf}}
 +  * Due Oct 11th - Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," MICRO 1999. {{:austin_diva99.pdf|pdf}}
 +
 +=====Lecture 16=====
 +  * Due Oct 14th - Patel, "Processor-Memory Interconnections for Multiprocessors," ISCA 1979. {{:patel_procmeminterconnect79.pdf|pdf}}
 +
 +  * Due Oct 16th - Moscibroda and Mutlu, "A Case for Bufferless Routing in On-Chip Networks," ISCA 2009. {{:moscibroda09.pdf|pdf}}
 +
 +=====Lecture 20=====
 +  * Due Oct 28th - Das et al., "Aergia: Exploiting Packet Latency Slack in On-Chip Networks," ISCA 2010. {{:das_aergia.pdf|pdf}}
 +  * Due Oct 28th - Dennis and Misunas, "A preliminary architecture for a basic data flow processor," ISCA 1974. {{:dennis74.pdf|pdf}}
 +
 +  * Due Oct 30th - Arvind and Nikhil, "Executing a program on the MIT tagged-token dataflow architecture," IEEE TC 1990. {{:arvind90.pdf|pdf}}
 +
 +=====Lecture 21=====
 +  * Due Nov 1st - Patt et al., "HPS, a new microarchitecture: rationale and introduction," MICRO 1985. {{:patt85.pdf|pdf}}
 +  * Due Nov 1st - Patt et al., "Critical issues regarding HPS, a high performance microarchitecture," MICRO 1985. {{:patt85-hpsissues.pdf|pdf}}
 +
 +=====Lecture 23=====
 +  * Due Nov 4th - Kung, “Why Systolic Architectures?,” IEEE Computer 1982. {{:kung_systolic82.pdf|pdf}}
 +
 +=====Lecture 24=====
 +  * Due Nov 13th - Mutlu and Moscibroda, “Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems,” ISCA 2008. {{:mutlu08-parbs.pdf|pdf}}
 +  * Due Nov 13th - Kim et al., “Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,” MICRO 2010. {{:kim10-tcm.pdf|pdf}}
 +
 +  * Due Nov 15th - Ebrahimi et al., “Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems,” ASPLOS 2010. {{:ebrahimi_throttle10.pdf|pdf}}
 +  * Due Nov 15th - Muralidhara et al., “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning,” MICRO 2011. {{:mcp_micro2011.pdf|pdf}}