Readings

Post your paper reviews for the papers marked [Review Required] on the paper review site . The expectations for these reviews are described in Recitation 1. You can view reviews by other students only after the deadline.

1. Onur Mutlu and Lavanya Subramanian, Research Problems and Opportunities in Memory Systems, Invited Article in Supercomputing Frontiers and Innovations (SUPERFRI), 2015. [Review Required]
2. Onur Mutlu, Rethinking the Systems We Design, Technical talk at A Computer Architecture Workshop: Visions for the Future (Celebrating Yale@75) (YALE@75), Austin, TX, September 2014 [Review Required]
3. Junwhan Ahn et al., A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. [Optional]
4. Vivek Seshadri et al., Fast Bulk Bitwise AND and OR in DRAM, IEEE Computer Architecture Letters (CAL), April 2015. [Review Required]

1. Smith, Task of the Referee, IEEE Computer 1990.
2. Hill and McKinley, Notes on Constructive and Positive Reviewing
3. Thomas Moscibroda and Onur Mutlu, Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007.

1. Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, Proceedings of the 42nd International Symposium on Computer Architecture(ISCA), Portland, OR, June 2015. [Review Required]
2. Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, GPUs and the Future of Parallel Computing, IEEE Micro 2011. [Review Required]
3. Jeffrey D. Ullman, Experiments as Research Validation: Have We Gone Too Far?, CACM 2015. [Review Required]
4. Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarungnirun, Chita Das, Mahmut Kandemir, Todd C. Mowry, and Onur Mutlu, A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. [Review Required]

1. Moore, Cramming more components onto integrated circuits, Electronics Magazine, 1965.
2. Kuhn, The structure of scientific revolutions, 1962.
3. Hill and McKinley, Notes on Constructive and Positive Reviewing
4. Levin and Redell, How (and how not) to write a good systems paper, OSR 1983.
5. Jones, How to Write a Great Research Paper
6. Fong, How to Write a CS Research Paper: A Bibliography
7. Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015.
8. Nickolls and Dally, The GPU Computing Era , IEEE Micro 2010.