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readings [2015/11/05 04:20] nandita [Optional Readings Mentioned in the Lecture] |
readings [2015/11/10 07:04] nandita [Optional Readings Mentioned in the Lecture] |
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| * Das et al., [[http://research.microsoft.com/en-us/um/people/moscitho/Publications/MICRO2009.pdf |Application-Aware Prioritization Mechanisms for On-Chip Networks]], //MICRO 2009// | * Das et al., [[http://research.microsoft.com/en-us/um/people/moscitho/Publications/MICRO2009.pdf |Application-Aware Prioritization Mechanisms for On-Chip Networks]], //MICRO 2009// | ||
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| + | =====Lecture 17===== | ||
| + | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// | ||
| + | * Suleman et al., [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]], //ASPLOS 2009// | ||
| + | * Gorchowski et al., [[http://dl.acm.org/citation.cfm?id=1032648.1033367 | Best of Both Latency and Throughput]], //ICCD 2004.// | ||
| + | * Meza et al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], // IEEE Comp. Arch. Letters, 2012.// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012.// | ||
| + | * Kim et al., [[http://users.ece.cmu.edu/~omutlu/pub/tcm_micro10.pdf|Thread Cluster Memory Scheduling]], //MICRO 2010.// | ||
| + | * Tendler et al., [[http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf | POWER4 system microarchitecture]], //IBM J R&D, 2002.// | ||
| + | * Kalla et al., [[http://www.ece.cmu.edu/~ece447/s12/lib/exe/fetch.php?media=wiki:kalla-2004.pdf|IBM Power5 Chip: A Dual-Core Multithreaded Processor]], //IEEE Micro 2004.// | ||
| + | * Konngetira et al., [[http://www.ece.cmu.edu/~ece742/f12/lib/exe/fetch.php?media=kongetira05_niagara.pdf| Niagara: A 32-Way Multithreaded SPARC Processor]], //IEEE Micro 2005// | ||
| + | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
| + | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// | ||