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This shows you the differences between two versions of the page.

--- readings [2015/10/28 17:03]
nandita [Review Set 6]
+++ readings [2015/11/05 04:20]
nandita [Optional Readings Mentioned in the Lecture]
@@ Line 199: / Line 199: @@
 ==== Review Set 7 ====
-  * Perais et al., [[http://people.irisa.fr/Arthur.Perais/data/ISCA'14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]], //ISCA 2014.// **[[Required]]**
+  * Perais et al., [[http://people.irisa.fr/Arthur.Perais/data/ISCA'14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]], //ISCA 2014.// **[Required]**
-  * Vijaykumar et al., [[https://engineering.purdue.edu/~vijay/papers/2002/srtr.pdf | Transient-Fault Recovery Using Simultaneous Multithreading]], //ISCA 2000.// **[[Required]]**
+  * Reinhardt et al., [[http://pages.cs.wisc.edu/~shubu/papers/isca2000-srt.pdf | Transient fault detection via simultaneous multithreading]], //ISCA 2000.// **[Required]**
-  * Constantinides et al. [[https://users.ece.cmu.edu/~omutlu/pub/ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]], //MICRO 2007.// **[[Required]]**
+  * Constantinides et al. [[https://users.ece.cmu.edu/~omutlu/pub/ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]], //MICRO 2007.// **[Required]**
+===== Recitation 10 =====
+==== Review Set 8 ====
+  * Mike O'Connor, [[https://www.ece.cmu.edu/~calcm/doku.php?id=seminars:seminar_11_03_15|High-bandwidth, Energy-efficient DRAM Architectures for GPU Systems]] , //CALCM Talk// **[Required]**
+===== Lecture 15 ======
+==== Optional Readings Mentioned in the Lecture ====
+  * Mutlu et al., [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //ISCA 2008.//
+  * Muralidhara et al., [[http://users.ece.cmu.edu/~omutlu/pub/memory-channel-partitioning-micro11.pdf|Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning]], //MICRO 2011.//
+  * Ebrahimi et al., [[http://users.ece.cmu.edu/~omutlu/pub/parallel-memory-scheduling_micro11.pdf|Parallel Application Memory Scheduling]], //MICRO 2011.//
+  * Wang et al., [[https://users.ece.cmu.edu/~omutlu/pub/architecture-aware-distributed-resource-management_vee15.pdf|A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters]],//VEE 2015.//
+  * Moscibroda et al., [[https://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks]], //USENIX Security 2007.//
+  * Mutlu et. al., [[https://users.ece.cmu.edu/~omutlu/pub/stfm_micro07-summary.pdf|Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors]], //MICRO 2007.//
+  * Kim et al., [[http://users.ece.cmu.edu/~omutlu/pub/atlas_hpca10.pdf|ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers]],//HPCA 2010.//
+  * Kim et al.,[[http://users.ece.cmu.edu/~omutlu/pub/tcm_micro10.pdf|Thread Cluster Memory Scheduling]], //MICRO 2010.//
+  * Ebrahimi et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]],   //ASPLOS 2010//
+===== Lecture 16 =====
+==== Optional Readings Mentioned in the Lecture ====
+  * Moscibroda et al., [[https://users.ece.cmu.edu/~omutlu/pub/bless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks]] , //ISCA 2009//
+  * Das et al., [[http://research.microsoft.com/en-us/um/people/moscitho/Publications/MICRO2009.pdf |Application-Aware Prioritization Mechanisms for On-Chip Networks]], //MICRO 2009//