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readings [2015/11/03 07:17] nandita [Review Set 8] |
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| * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Optional]** | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Optional]** | ||
| * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.// **[Optional]** | * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.// **[Optional]** | ||
| + | |||
| + | ===== Lecture 9 ===== | ||
| ==== Optional Readings Mentioned in the Lecture ==== | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Ipek et al., [[http://m3.csl.cornell.edu/papers/isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach]], //ISCA 2008// | ||
| + | * J. Zhao et al., [[https://users.ece.cmu.edu/~omutlu/pub/firm-persistent-memory-scheduling_micro14.pdf | FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems]], //MICRO 2014.// | ||
| + | * M. Qureshi et al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable high performance main memory system using phase-change memory technology]], //ISCA 2009.// | ||
| + | * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.// | ||
| + | * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
| + | * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | ||
| + | * Kultursay et al., [[https://users.ece.cmu.edu/~omutlu/pub/sttram_ispass13.pdf | Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative]], //ISPASS 2013.// | ||
| + | * Meza et al., [[http://research.ihost.com/weed2013/papers/storage_memory.pdf | A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory]], //WEED 2013.// | ||
| + | |||
| + | ===== Recitation 6 ===== | ||
| + | |||
| + | ==== Review Set 6 ==== | ||
| + | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Required]** | ||
| + | * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.// **[Required]** | ||
| + | * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010// **[Required]** | ||
| + | |||
| + | ===== Recitation 9 ===== | ||
| + | |||
| + | ==== Review Set 7 ==== | ||
| + | * Perais et al., [[http://people.irisa.fr/Arthur.Perais/data/ISCA'14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]], //ISCA 2014.// **[Required]** | ||
| + | * Reinhardt et al., [[http://pages.cs.wisc.edu/~shubu/papers/isca2000-srt.pdf | Transient fault detection via simultaneous multithreading]], //ISCA 2000.// **[Required]** | ||
| + | * Constantinides et al. [[https://users.ece.cmu.edu/~omutlu/pub/ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]], //MICRO 2007.// **[Required]** | ||
| + | |||
| + | ===== Recitation 10 ===== | ||
| + | ==== Review Set 8 ==== | ||
| + | * Mike O'Connor, [[https://www.ece.cmu.edu/~calcm/doku.php?id=seminars:seminar_11_03_15|High-bandwidth, Energy-efficient DRAM Architectures for GPU Systems]] , //CALCM Talk// **[Required]** | ||
| + | |||
| + | ===== Lecture 15 ====== | ||
| + | |||
| + | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Mutlu et al., [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //ISCA 2008.// | ||
| + | * Muralidhara et al., [[http://users.ece.cmu.edu/~omutlu/pub/memory-channel-partitioning-micro11.pdf|Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning]], //MICRO 2011.// | ||
| + | * Ebrahimi et al., [[http://users.ece.cmu.edu/~omutlu/pub/parallel-memory-scheduling_micro11.pdf|Parallel Application Memory Scheduling]], //MICRO 2011.// | ||
| + | * Wang et al., [[https://users.ece.cmu.edu/~omutlu/pub/architecture-aware-distributed-resource-management_vee15.pdf|A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters]],//VEE 2015.// | ||
| + | * Moscibroda et al., [[https://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks]], //USENIX Security 2007.// | ||
| + | * Mutlu et. al., [[https://users.ece.cmu.edu/~omutlu/pub/stfm_micro07-summary.pdf|Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors]], //MICRO 2007.// | ||
| + | * Kim et al., [[http://users.ece.cmu.edu/~omutlu/pub/atlas_hpca10.pdf|ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers]],//HPCA 2010.// | ||
| + | * Kim et al., [[http://users.ece.cmu.edu/~omutlu/pub/tcm_micro10.pdf|Thread Cluster Memory Scheduling]], //MICRO 2010.// | ||
| + | * Ebrahimi et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], // ASPLOS 2010// | ||
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