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readings [2015/09/29 05:46] nandita [Optional Readings Mentioned in the Lecture] |
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* Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], //HPCA 2013// | * Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], //HPCA 2013// | ||
* Wilkes, [[https://www.cs.princeton.edu/courses/archive/fall10/cos375/WilkesCacheElectronics.pdf | Slave Memories and Dynamic Storage Allocation,]] //IEEE Trans. On Electronic Computers, 1965.// | * Wilkes, [[https://www.cs.princeton.edu/courses/archive/fall10/cos375/WilkesCacheElectronics.pdf | Slave Memories and Dynamic Storage Allocation,]] //IEEE Trans. On Electronic Computers, 1965.// | ||
+ | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
+ | * Yoongu Kim et al., [[https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf| A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM]], //ISCA 2012// | ||
+ | * Rau, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.7149&rep=rep1&type=pdf | Pseudo-randomly Interleaved Memory]],// ISCA 1991// | ||
+ | * Lee et al., [[https://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf | DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems]], //HPS Technical Report, April 2010.// | ||