This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
readings [2015/09/29 05:41] nandita [Optional Readings Mentioned in the Lecture] |
readings [2015/09/29 05:50] nandita [Optional Readings Mentioned in the Lecture] |
||
|---|---|---|---|
| Line 152: | Line 152: | ||
| * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
| * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
| - | + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | |
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
| + | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
| + | * Subramanian et al., [[The Application Slowdown Model]], //MICRO 2015.// | ||
| + | * Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], //HPCA 2013// | ||
| + | * Wilkes, [[https://www.cs.princeton.edu/courses/archive/fall10/cos375/WilkesCacheElectronics.pdf | Slave Memories and Dynamic Storage Allocation,]] //IEEE Trans. On Electronic Computers, 1965.// | ||
| + | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
| + | * Yoongu Kim et al., [[https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf| A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM]], //ISCA 2012// | ||
| + | * Rau, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.7149&rep=rep1&type=pdf | Pseudo-randomly Interleaved Memory]],// ISCA 1991// | ||