This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
readings [2015/09/28 16:37] nandita [Review Set 1 (due 3 PM)] |
readings [2015/09/29 05:26] nandita [Papers Mentioned in the Lecture (Not in Slides)] |
||
|---|---|---|---|
| Line 24: | Line 24: | ||
| ===== Recitation 2 ===== | ===== Recitation 2 ===== | ||
| - | ==== Review Set 2 (due 3 PM)==== | + | ==== Review Set 2==== |
| - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | ||
| - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | ||
| Line 51: | Line 51: | ||
| ===== Recitation 3 ===== | ===== Recitation 3 ===== | ||
| - | ==== Review Set 3 (due 3 PM) ==== | + | ==== Review Set 3 ==== |
| - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | ||
| - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
| Line 137: | Line 137: | ||
| * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | ||
| + | ===== Lecture 5 ===== | ||