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readings [2015/09/23 16:17] nandita [Optional Readings Mentioned in the Lecture] |
readings [2015/10/28 17:03] nandita [Review Set 6] |
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| ===== Recitation 1 ===== | ===== Recitation 1 ===== | ||
| - | ==== Review Set 1 (due 3 PM)==== | + | ==== Review Set 1==== |
| - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
| Systems]], //Invited Article in Supercomputing Frontiers and Innovations | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
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| ===== Recitation 2 ===== | ===== Recitation 2 ===== | ||
| - | ==== Review Set 2 (due 3 PM)==== | + | ==== Review Set 2==== |
| - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | ||
| - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | ||
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| ===== Recitation 3 ===== | ===== Recitation 3 ===== | ||
| - | ==== Review Set 3 (due 3 PM) ==== | + | ==== Review Set 3 ==== |
| - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | ||
| - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
| Line 106: | Line 106: | ||
| * Rachata Ausavarungnirun et. al., [[http://users.ece.cmu.edu/~omutlu/pub/MeDiC-for-GPGPUs_pact15.pdf | Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance]], //PACT 2015// **[Review Required]** | * Rachata Ausavarungnirun et. al., [[http://users.ece.cmu.edu/~omutlu/pub/MeDiC-for-GPGPUs_pact15.pdf | Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance]], //PACT 2015// **[Review Required]** | ||
| * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]** | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]** | ||
| - | * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Review Required]** | + | * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Optional]** |
| ==== Optional Readings Mentioned in the Lecture ==== | ==== Optional Readings Mentioned in the Lecture ==== | ||
| Line 118: | Line 118: | ||
| * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
| * Junwhan Ahn et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], //ISCA 2015.// | * Junwhan Ahn et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], //ISCA 2015.// | ||
| + | * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.// | ||
| + | * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.// | ||
| + | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
| + | * Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | ||
| + | * Cai et. al. [[http://www.istc-cc.cmu.edu/publications/papers/2013/flash-programming-interference_iccd13.pdf | Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation]]. //ICCD 2013// | ||
| + | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], //Intel Technology Journal 2013// | ||
| + | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/neighbor-assisted-error-correction-in-flash_sigmetrics14.pdf | Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories]], //SIGMETRICS 2014// | ||
| + | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
| + | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
| + | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
| + | ==== Papers Mentioned in the Lecture (Not in Slides) ==== | ||
| + | * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010// | ||
| + | * Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// | ||
| + | * Raoux et. al., [[ http://researcher.watson.ibm.com/researcher/files/us-gwburr/PCM_IBMJRD.pdf | Phase-change random access memory: A scalable technology]], //IBM JRD 2008// | ||
| + | * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | ||
| - | + | ===== Lecture 5 ===== | |
| + | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
| + | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
| + | (SUPERFRI), 2015.// | ||
| + | * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010// | ||
| + | * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.// | ||
| + | * Yoongu Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], //ISCA 2014.// | ||
| + | * Seaborn et.al., [[https://www.blackhat.com/docs/us-15/materials/us-15-Seaborn-Exploiting-The-DRAM-Rowhammer-Bug-To-Gain-Kernel-Privileges.pdf | Exploiting the DRAM rowhammer bug to gain kernel privileges]], //2015// | ||
| + | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// | ||
| + | * Liu et al., [[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf | RAIDR: Retention-Aware Intelligent DRAM Refresh]],// ISCA 2012.// | ||
| + | * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.// | ||
| + | * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.// | ||
| + | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
| + | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
| + | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
| + | * Subramanian et al., [[The Application Slowdown Model]], //MICRO 2015.// | ||
| + | * Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], //HPCA 2013// | ||
| + | * Wilkes, [[https://www.cs.princeton.edu/courses/archive/fall10/cos375/WilkesCacheElectronics.pdf | Slave Memories and Dynamic Storage Allocation,]] //IEEE Trans. On Electronic Computers, 1965.// | ||
| + | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
| + | * Yoongu Kim et al., [[https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf| A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM]], //ISCA 2012// | ||
| + | * Rau, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.7149&rep=rep1&type=pdf | Pseudo-randomly Interleaved Memory]],// ISCA 1991// | ||
| + | * Lee et al., [[https://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf | DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems]], //HPS Technical Report, April 2010.// | ||
| + | * Ipek et al., [[http://m3.csl.cornell.edu/papers/isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach]], //ISCA 2008// | ||
| + | * J. Zhao et al., [[https://users.ece.cmu.edu/~omutlu/pub/firm-persistent-memory-scheduling_micro14.pdf | FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems]], //MICRO 2014.// | ||
| + | * M. Qureshi et al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable high performance main memory system using phase-change memory technology]], //ISCA 2009.// | ||
| + | |||
| + | |||
| + | ===== Recitation 5 ===== | ||
| + | ==== Review Set 5 ==== | ||
| + | * Justin Meza et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Review Required]** | ||
| + | * Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], // Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May 2013.// **[Review Required]** | ||
| + | * Edmund B. Nightingale et al, [[http://eurosys2011.cs.uni-salzburg.at/pdf/eurosys2011-nightingale.pdf | Cycles, cells and platters: an empirical analysis of hardware failures on a million consumer PCs]], //Eurosys 2011.// **[Review Required]** | ||
| + | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Optional]** | ||
| + | * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.// **[Optional]** | ||
| + | |||
| + | ===== Lecture 9 ===== | ||
| + | |||
| + | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Ipek et al., [[http://m3.csl.cornell.edu/papers/isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach]], //ISCA 2008// | ||
| + | * J. Zhao et al., [[https://users.ece.cmu.edu/~omutlu/pub/firm-persistent-memory-scheduling_micro14.pdf | FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems]], //MICRO 2014.// | ||
| + | * M. Qureshi et al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable high performance main memory system using phase-change memory technology]], //ISCA 2009.// | ||
| + | * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.// | ||
| + | * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
| + | * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | ||
| + | * Kultursay et al., [[https://users.ece.cmu.edu/~omutlu/pub/sttram_ispass13.pdf | Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative]], //ISPASS 2013.// | ||
| + | * Meza et al., [[http://research.ihost.com/weed2013/papers/storage_memory.pdf | A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory]], //WEED 2013.// | ||
| + | |||
| + | ===== Recitation 6 ===== | ||
| + | |||
| + | ==== Review Set 6 ==== | ||
| + | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Required]** | ||
| + | * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.// **[Required]** | ||
| + | * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010// **[Required]** | ||
| + | |||
| + | ===== Recitation 9 ===== | ||
| + | |||
| + | ==== Review Set 7 ==== | ||
| + | * Perais et al., [[http://people.irisa.fr/Arthur.Perais/data/ISCA'14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]], //ISCA 2014.// **[[Required]]** | ||
| + | * Vijaykumar et al., [[https://engineering.purdue.edu/~vijay/papers/2002/srtr.pdf | Transient-Fault Recovery Using Simultaneous Multithreading]], //ISCA 2000.// **[[Required]]** | ||
| + | * Constantinides et al. [[https://users.ece.cmu.edu/~omutlu/pub/ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]], //MICRO 2007.// **[[Required]]** | ||