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readings [2015/09/23 16:03] nandita [Review Set 4] |
readings [2015/09/23 16:38] nandita [Optional Readings Mentioned in the Lecture] |
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| * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]** | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]** | ||
| * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Review Required]** | * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Review Required]** | ||
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| + | ==== Optional Readings Mentioned in the Lecture ==== | ||
| + | * Kevin Chang et. al., [[ http://www.pdl.cmu.edu/ftp/associated/sbacpad2012_hat.pdf | HAT: Heterogeneous Adaptive Throttling for On-Chip Networks]], //SBAC-PAD 2012// | ||
| + | * Wilson W. L. Fung et. al., [[ https://www.ece.ubc.ca/~aamodt/papers/wwlfung.micro2007.pdf | Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow]], //MICRO 2007// | ||
| + | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
| + | * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015// | ||
| + | * Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
| + | Parallel Graph Processing]], //ISCA 2015.// | ||
| + | * Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | ||
| + | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
| + | * Junwhan Ahn et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], //ISCA 2015.// | ||
| + | * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.// | ||
| + | * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.// | ||
| + | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
| + | * Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | ||
| + | * Cai et. al. [[http://www.istc-cc.cmu.edu/publications/papers/2013/flash-programming-interference_iccd13.pdf | Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation]]. //ICCD 2013// | ||
| + | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], //Intel Technology Journal 2013// | ||
| + | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/neighbor-assisted-error-correction-in-flash_sigmetrics14.pdf | Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories]], //SIGMETRICS 2014// | ||
| + | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
| + | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
| + | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
| + | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
| + | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
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